PC97338 datasheet(196/221 Pages) NSC

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TABLE 107. Clock Multiplier Encoding Options

From this point on, bits 1 and 0 of the CLK register

are read-only. The value of the clock source can

not be changed, except by a total power-off and

power-on cycle. However, the on-chip clock multi-

plier can be disabled at any time.

2. If the external clock source is 14.31818 MHz or 24

MHz:

— Enable the on-chip clock multiplier.

— Poll bit 3 of the CLK register while the clock

multiplier is stabilizing.

— When bit 3 of CLK is set to 1, go to step 3.

If the external clock source is 48 MHz, do not en-

able the clock multiplier.

3. Enable any module of the chip.

7.2.3

SCC1 and SCC2 Power-Up

The clock signal to the SCCs is controlled by the FER

and PTR configuration registers.

To restore the clock signal to one or both SCCs, the

following must both be true:

• The appropriate enable bits, bits 2 and 1 of FER

for SCC2 and SCC1, respectively must be set to

• The power-down bit, bit 0 of PTR, must be 0.

If the on-chip clock multiplier stopped, allow time

(maximum 2.4 msec) for multiplier stabilization before

sending any data or signaling that the receiver chan-

nel is ready. The stabilization period can be sensed

by reading the Main Status Register in the FDC, if the

FDC is being powered up. (The Request for Master bit

(RQM) is not set for approximately 2.4 msec). If the

FDC is not powered up but, either one of the SCCs is

being powered up, then, software must generate a

delay of 2.4 msec. Stabilization of multiplier can also

be sensed by putting any of the enabled SCCs into lo-

cal loopback mode and sending bytes until they are

received correctly.

7.2.4

FDC Power-Up

The clock signal to the FDC is controlled by the con-

figuration registers, the FDC MODE command and

the Data Rate Select Register (DSR).

To restore the clock signal to the FDC, both of the fol-

lowing conditions must be true:

• Bit 3 of FER must be set to 1.

• The power-down bit, bit 0 of PTR, must be 0.

In addition to these conditions, do one of the following

to initiate the recovery from power-down mode:

• Read the Main Status Register (MSR) until the

RQM bit, bit 7, is set to 1.

• Set the software reset bit, bit 7 or the Data Rate

Select Register (DSR), to 1.

• Write the following to the reset bit, bit 2 or the Dig-

ital Output Register (DOR):

— Set it to 1.

— Clear it to 0.

• Read the Data Register and the Main Status Reg-

ister until the RQM bit is set to 1.

External

Clock on

Pin X1

(MHz)

CLK Register (Index 51h)

Valid Clock

Multiplier

Status

Clock

Multiplier

Enable

Chip Clock

Source

14.31818

0 = Reset

1 = Stable

Always 0

Reserved

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