PC97338 datasheet(135/221 Pages) NSC

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4.4.3

Hardware Operation in ECP

Modes

The ZWS signal is asserted by the ECP when ECP

modes are enabled, and an ECP register is accessed

by system PIO instructions, thus using a system zero

wait states cycle (except during read cycles from

ECR).

The ECP uses an internal clock, which can be frozen

to reduce power consumption during power down. In

this power-down state the DMA is disabled, all inter-

rupts (except ACK) are masked, and the FIFO regis-

ters are not accessible (access is ignored). The other

ECP registers are unaffected by power-down and are

always accessible when the ECP is enabled. During

power-down the FIFO status and contents become in-

accessible, and the system reads bit 2 of ECR as 0,

bit 1 of ECR as 1 and bit 0 of ECR as 1, regardless of

the actual values of these bits. The FIFO status and

contents are not lost, however, and when the clock

activity resumes, the values of these bits resume their

designated functions.

When the clock is frozen, an on-going ECP cycle may

be corrupted, but the next ECP cycle will not start

even if the FIFO is not empty in the forward direction,

or not full in the backward direction. If the ECP clock

starts or stops toggling during a system cycle that ac-

cesses the FIFO, the cycle may yield wrong data.

ECP output signals are inactive when the ECP is dis-

abled.

Only the FIFO, DMA and RLE do not function when

the clock is frozen. All other registers are accessible

and functional. The FIFO, DMA and RLE are affected

by ECR modifications, i.e., they are reset when exits

from modes 010 or 011 are carried out even while the

clock is frozen.

4.4.4

ECP Modes Parallel Port Register

Bitmaps

543

Reset

Required

ECP Data Register

(DATAR)

Offset 000h

543

Reset

Required

ECP Address Register

(AFIFO)

Offset 000h

321

Reset

Required

ECP Status Register

(DSR)

Offset 001h

Reserved

SLCT Status

PE Status

ACK Status

Printer Status

ERR Status

321

Reset

Required

ECP Control

Offset 002h

Printer Initialization Control(INIT)

Interrupt Enable

Direction Control

Reserved

Data Strobe Control

Automatic Line Feed Control

Parallel Port Input Control

Bits 7-5 of ECR = 000 or 001

Bits 7-5 of ECR = 011

All ECP Modes

Reserved

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