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STA333IS датащи(PDF) 29 Page - STMicroelectronics

номер детали STA333IS
подробное описание детали  100 dB SNR and dynamic range
PDF  43 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STA333IS датащи(HTML) 29 Page - STMicroelectronics

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STA333IS
Register description
LRCK double trigger protection
The LDTE bit actively prevents double triggering of LRCLK.
Auto EAPD on clock loss
When active, the ECLE bit will issue a device power-down signal (EAPD) on clock loss
detection.
IC power-down
The PWDN register is used to put the IC in a low-power state. When PWDN is 0, the output
begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down
the power stage, then the master clock to all internal hardware except the I2C block is gated.
This puts the IC in a very low power consumption state.
External amplifier power down
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled).
Table 35. LRCK double trigger protection
Bit
R/W
RST
Name
Description
4
R/W
1
LDTE
LRCLK double trigger protection enable
Table 36. Auto EAPD on clock loss
Bit
R/W
RST
Name
Description
5
R/W
0
ECLE
Auto EAPD on clock loss
Table 37. Power-down
Bit
R/W
RST
Name
Description
6R/W
1PWDN
0: power-down, low-power condition
1: normal operation
Table 38. External amplifier power-down
Bit
R/W
RST
Name
Description
7
R/W
1
EAPD
0: external power stage power-down active
1: normal operation



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