STA333IS datasheet(16/43 Pages) STMICROELECTRONICS

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I2C bus specification

STA333IS

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DocID022855 Rev 3

I2C bus specification

The STA333IS supports the I2C protocol via the input ports SCL and SDA. This protocol

defines any device that sends data to the bus as a transmitter and any device that reads the

data as a receiver. The device that controls the data transfer is known as the master and the

other as the slave. The master always starts the transfer and provides the serial clock for

synchronization. The STA333IS is always a slave device in all of its communications. It

supports up to 400 kb/s (fast-mode bit rate).

4.1

Communication protocol

4.1.1

Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. An SDA

transition while the clock is high is used to identify a START or STOP condition.

4.1.2

Start condition

START is identified by a high-to-low transition of the data bus SDA signal while the clock

signal SCL is stable in the high state. A START condition must precede any command for

data transfer.

4.1.3

Stop condition

STOP is identified by a low-to-high transition of the data bus SDA signal while the clock

signal SCL is stable in the high state. A STOP condition terminates communication between

the STA333IS and the bus master.

4.1.4

Data input

During data input the STA333IS samples the SDA signal on the rising edge of clock SCL.

For correct device operation the SDA signal must be stable during the rising edge of the

clock and the data can change only when the SCL line is low.

4.2

Device addressing

To start communication between the master and the STA333IS, the master must initiate a

start condition. Following this, the master sends to the SDA line 8 bits (MSB first)

corresponding to the device select address and read or write mode.

The 7 most significant bits are the device address identifiers, corresponding to the I2C bus

definition. In the STA333IS the I2C interface has device address 0x38.

The 8th bit (LSB) identifies the read or write operation RW, this bit is set to 1 for read mode

and 0 for write mode. After a START condition the STA333IS identifies the device address

on the SDA bus and if a match is found, acknowledges the identification during the 9th bit

time. The byte following the device identification byte is the internal space address.

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