FREQ datasheet(19/56 Pages) FUJITSU

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MB39A214A

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FUJITSU SEMICONDUCTOR CONFIDENTIAL

DS405-00007-1v0-E

(9) Under Voltage Protection (UVP)

This function stops the output voltage when the output voltage has lowered, and protects devices connected

to the output.

1. Using UVP Comp, this function makes a comparison between the voltage which is 0.7 times (Typ) of

the internal reference voltage REF1, REF2 (0.7 V), and the feedback voltage for the FB1 pin (pin 4) and

the FB2 pin (pin 9).

2. If the feedback voltage mentioned in 1 detects the higher state by 150µs (Typ) or more, the operations

below will be performed.

Set the RS latch.

Set the DRVH1 pin (pin 24) and the DRVH2 pin (pin 13) to the “L” level.

Set the DRVL1 pin (pin 22) and the DRVL2 pin (pin 15) to the “L” level.

These operations fix the high-side FET to the off state and the low-side FET to the off state for both

channels of the DC/DC converter, and stops switching (latch stop). The discharge operation is then carried

out to discharge the output capacitor (The discharge operation continues until the state of the under-voltage

protection is released).

The under-voltage protection state can be cancelled by setting both the EN1 pin (pin 2) and EN2 pin (pin 11)

to the “L” level or reducing the VCC power once until the bias voltage (VB) falls below VTHL of UVLO.

VOUT1

FB1

DRVH1

DRVL1

CS1

VOUT2

FB2

DRVH2

DRVL2

CS2

EN1, EN2

0 V

INTREF

UVLO VTHL

150 µs

0 V

Output voltage

setting value

Standby

Less than 15 µs

Cancellation of over-voltage protection state by EN = "L".

INTREF

0.8

INTREF

0.7

Output voltage

setting value

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