FREQ datasheet(34/56 Pages) FUJITSU

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MB39A214A

Limitation : development tool vendor use only

FUJITSU SEMICONDUCTOR CONFIDENTIAL

DS405-00007-1v0-E

If the formula above has been already satisfied and then a low ON resistance FET as possible is used for the

low-side FET, the loss is effectively decreased. Especially, it works dramatically in the low on duty mode.

The loss of the low-side FET can be calculated by the following formula.

VOUT

PSyncFET = PRON_Sync = IOUT_MAX

(1 –

VIN

)

RON_Sync

PSyncFET

: Low-side FET loss [W]

PRON_Sync : Low-side FET conduction loss [W]

IOUT_MAX : Maximum load current [A]

VIN

: Power supply voltage [V]

VOUT

: Output voltage [V]

RON_Sync : ON resistance of low-side FET [Ω]

Turn-on and turn-off voltage of the low-side FET is generally small and the switching loss is small enough

to ignore, so that is omitted here.

Especially, when turning on the high-side FET under the high power supply voltage condition, the

rush-current might be generated by according to self-turn-on of the low-side FET. The parasitic capacitor

value of the low-side FET needs to satisfy the following conditions.

Crss

VTH_Sync >

Ciss

VIN

VTH_Sync

: Threshold voltage of low-side FET [V]

Crss

: Parasitic feedback capacitance of low-side FET [F]

Ciss

: Parasitic input capacitance of low-side FET [F]

VIN

: Power supply voltage [V]

Also approaches of adding a capacitor close between the gate source pins of the low-side FET or adding

resistor between the BST pin and the boost capacitor, and so on are effective as a countermeasure of the

self-turn-on(adding resistor between the BST pin and the boost capacitor is also effective to adjust turn-on

time of the high-side FET).

This device monitors the gate voltage of the switching FET and optimizes the dead time. If the dumping

resistor is inserted among DRVH, DRVL and the switching FET gate to adjust turn-on and turn-off time of

the switching FET, this function might malfunction. In this device, resistor should not be connected among

the DRVH pin, the DRVL pin of IC and the switching FET gate, and should be connected by low

impedance as possible.

The gate drive power of the switching FET is supplied from LDO (VB) of IC inside. Select switching FET

so that the total amount of the switching FET electric charge for 2 channels (QG_Total1, QG_Total2)

satisfies the following formula.

IVB_MAX > QG_Total1

fOSC1 + QG_Total2

fOSC2

IVB_MAX : VB load current upper limit value (see the following graph) [A]

QG_Total1 : Total quantity of charge for the high-side FET and the low-side FET of each CH1 [C]

QG_Total2 : Total quantity of charge for the high-side FET and the low-side FET of each CH2 [C]

fOSC1

: CH1Switching frequency [Hz]

fOSC2

: CH2 Switching frequency [Hz]

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