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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DS2196 датащи(PDF) 28 Page - Dallas Semiconductor |
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DS2196 датащи(HTML) 28 Page - Dallas Semiconductor |
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28 / 157 page  DS2196 28 of 157 The factory in testing the DS2196 uses the two Test Registers at addresses 09 and 7D hex. On power–up, the Test Registers should be set to 00 hex in order for the DS2196 to operate properly. RCR1A: RECEIVE CONTROL REGISTER 1 FRAMER A (Address = 2B Hex) (MSB) (LSB) LCVCRF ARC OOF1 OOF2 SYNCC SYNCT SYNCE RESYNC SYMBOL POSITION NAME AND DESCRIPTION LCVCRF RCR1A.7 Line Code Violation Count Register Function Select. 0 = do not count excessive 0’s 1 = count excessive 0’s ARC RCR1A.6 Auto Resync Criteria. 0 = Resync on OOF or RCL event 1 = Resync on OOF only OOF1 RCR1A.5 Out Of Frame Select 1. 0 = 2/4 frame bits in error 1 = 2/5 frame bits in error OOF2 RCR1A.4 Out Of Frame Select 2. 0 = follow RCR1.5 1 = 2/6 frame bits in error SYNCC RCR1A.3 Sync Criteria. In D4 Framing Mode. 0 = search for Ft pattern, then search for Fs pattern 1 = cross couple Ft and Fs pattern In ESF Framing Mode. 0 = search for FPS pattern only 1 = search for FPS and verify with CRC6 SYNCT RCR1A.2 Sync Time. 0 = qualify 10 bits 1 = qualify 24 bits SYNCE RCR1A.1 Sync Enable. 0 = auto resync enabled 1 = auto resync disabled RESYNC RCR1A.0 Resync. When toggled from low to high, a resynchronization of the receive side framer is initiated. Must be cleared and set again for a subsequent resync. |
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