DS2196 datasheet(27/157 Pages) DALLAS

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DS2196

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5. PARALLEL PORT

The DS2196 is controlled via either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an

external microcontroller or microprocessor. The DS2196 can operate with either Intel or Motorola bus

timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola

timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in

the AC Electrical Characteristics in Section 22 for more details.

6. CONTROL, ID, AND TEST REGISTERS

Each framer in the DS2196 is configured via a set of eleven control registers. Typically, the control

registers are only accessed when the system is first powered up. Once the DS2196 has been initialized,

the control registers will only need to be accessed when there is a change in the system configuration.

There are two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and

TCR2), and seven Common Control Registers (CCR1 to CCR7). Each of the eleven registers are

described in this section. There is a device Identification Register (IDR) at address 0Fh. The MSB of

this read–only register is fixed to a 0 indicating that a T1 device is present. The next 3 MSBs are used to

indicate which T1 device is present. The lower 4 bits of the IDR are used to display the die revision of

the chip.

Power-Up Sequence

The DS2196 does not automatically clear its register space on power–up. After the supplies are stable,

the register space should be configured for operation by writing to all of the internal registers. This

includes setting the Test and all unused registers to 00Hex.

This can be accomplished using a two-pass approach.

1. Clear DS2196 register space by writing 00h to the addresses 00h through 0FFh.

2. Program required registers to achieve desired operating mode.

IDR: DEVICE IDENTIFICATION REGISTER (Address = 0F Hex)

(MSB)

(LSB)

0011

ID3

ID2

ID1

ID0

SYMBOL

POSITION

NAME AND DESCRIPTION

0IDR.7

Chip ID Bit 3. MSB of DS2196 identification code. Set to 0.

0IDR.6

Chip ID Bit 2. DS2196 identification code. Set to 0.

1IDR.5

Chip ID Bit 1. DS2196 identification code. Set to 1.

1IDR.4

Chip ID Bit 0. LSB of DS2196 identification code. Set to 1.

ID3

IDR.3

Chip Revision Bit 3. MSB of a decimal code that represents

the chip revision.

ID2

IDR.1

Chip Revision Bit 2.

ID1

IDR.2

Chip Revision Bit 1.

ID0

IDR.0

Chip Revision Bit 0. LSB of a decimal code that represents

the chip revision.

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