ADF4356 datasheet(33/35 Pages) AD

33 / 35 page

Data Sheet

ADF4356

Rev. 0 | Page 33 of 35

APPLICATIONS INFORMATION

POWER SUPPLIES

The ADF4356 contains four multiband VCOs that cover an

octave range of frequencies. To ensure the best performance, it is

vital to connect a low noise regulator, such as the ADM7150 or

the ADM7170 to the VVCO pin. Connect the same regulator to

package pins VVCO, VREGVCO, and VP.

For the 3.3 V supply pins, use two ADM7170 regulators, one for

the DVDD and AVDD supplies and one for VRF. Figure 43 shows

the recommended connections.

PRINTED CIRCUIT BOARD (PCB) DESIGN

GUIDELINES FOR A CHIP-SCALE PACKAGE

The lands on the 32-lead, lead frame chip scale package are

rectangular. The PCB pad for these lands must be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. Center each land on the pad to

maximize the solder joint size.

The bottom of the chip scale package has a central exposed

thermal pad. The thermal pad on the PCB must be at least as

large as the exposed pad. On the PCB, there must be a minimum

clearance of 0.25 mm between the thermal pad and the inner

edges of the pad pattern. This clearance ensures the avoidance

of shorting.

To improve the thermal performance of the package, use thermal

vias on the PCB thermal pad. If vias are used, incorporate them

into the thermal pad at the 1.2 mm pitch grid. The via diameter

must be between 0.3 mm and 0.33 mm, and the via barrel must

be plated with 1 oz. of copper to plug the via.

For a microwave PLL and VCO synthesizer, such as the ADF4356,

take care with the board stack-up and layout. Do not consider

using FR4 material because it is too lossy above 3 GHz. Instead,

Rogers 4350, Rogers 4003, or Rogers 3003 dielectric material is

suitable.

Take care with the RF output traces to minimize discontinuities

and ensure the best signal integrity. Via placement and grounding

are critical.

100Ω

VOUT = 5.0V

VIN = 6.0V

VOUT

REF

GND

REF_SENSE

VREG

BYP

OFF

VIN

COUT

1µF

CIN

1µF

CREG

10µF

CBYP

1µF

430Ω

68Ω

VRF = 3.3V

VIN = 6.0V

VOUT

REF

GND

REF_SENSE

VREG

BYP

OFF

VIN

COUT

1µF

CIN

1µF

CREG

10µF

CBYP

1µF

VOUT = 3.3V

VIN = 6.0V

VOUT

REF

GND

REF_SENSE

VREG

BYP

OFF

VIN

COUT

1µF

CIN

1µF

CREG

10µF

CBYP

1µF

ADF4356

ADM7150

1nF

FREFIN

REFINA

REFINB

REFOUTB+

REFOUTB–

REFOUTA+

VRF

1nF

7.5nH

REFOUTA–

CLK

DATA

FREFIN

1nF

NIC

CPGND

SDGND

AGNDRF

13 18 21

AGND

VBIAS

VREF

VREGVCO

0.1µF

10pF

VVCO VP

AVDD

DVDD

AVDD CE PDBRF VRF CREG1CREG2 MUXOUT

100nF

VTUNE 20

CPOUT 7

100nF

0.1µF

10pF

0.1µF

33nF

6800pF

1µF

10pF

ADM7150

LOCK DETECT

Figure 43. Power Supplies

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