Data Sheet

ADF4356

Rev. 0 | Page 27 of 35

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2

DB1

DB0

00

0

00

RESERVED

CONTROL

BITS

11

0

0

0

0

00

00

C3(0) C2(1) C1(0)

C4(1)

0

0

0

AE1

AE2

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

ADC

CLOCK DIVIDER

AD8

AD7

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

AD2

AD1 ADC CLK DIV

00

0

1

1

00

1

0

2

..

.

.

.

..

.

.

.

..

.

.

.

1

1

0

0

252

1

1

0

1

253

1

1

1

0

254

1

1

1

1

255

AE1

ADC

0DISABLED

1ENABLED

AE2

ADC CONVERSION

0DISABLED

1ENABLED

Figure 38. Register 10

REGISTER 10

Control Bits

With Bits[C4:C1] set to 1010, Register 10 is programmed.

Figure 38 shows the input data format for programming this

register.

Reserved

Bits[DB31:DB14] are reserved. Bits[DB23:DB22] must be set to

11, and all other bits in this range must be set to 0.

ADC Clock Divider (ADC_CLK_DIV)

An on-board analog-to-digital converter (ADC) determines the

ADF4356 environment. The ADC ensures that the initial tuning

voltage in any application is chosen correctly to avoid any

temperature drift issues.

The ADC uses a clock that is equal to the output of the R

counter (or the PFD frequency) divided by ADC_CLK_DIV.

AD8 to AD1 (Bits[DB13:DB6]) set the value of this divider. On

power-up, the R counter is not programmed; however, in these

power-up cases, it defaults to R = 1.

Choose the value such that

where ceiling() is a function that rounds up to the nearest

integer.

so that the ADC clock frequency is 99.417 kHz.

If ADC_CLK_DIV is greater than 255, set it to 255.

ADC Conversion Enable

AE2 (Bit DB5) ensures that the ADC performs a conversion

when a write to Register 10 is performed. It is recommended to

enable this mode.

ADC Enable

AE1 (Bit DB4), when set to 1, powers up the ADC for the

always use this function.