Data Sheet

ADF4356

Rev. 0 | Page 25 of 35

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9 DB8

DB7

DB6

DB5 DB4

DB3

DB2

DB1

DB0

0

0

0

0

0

0

0

0

0

0

0

LD1

C3(1) C2(1) C1(1)

CONTROL

BITS

RESERVED

LD3

LD2

FRACTIONAL-N LD PRECISION

0

0

5.0ns

0

1

6.0ns

1

0

8.0ns

1

1

12.0ns

LD1

0

FRACTIONAL-N

1

INTEGER-N (2.9ns)

C4(0)

LOCK DETECT MODE

LD2

LD3

LOL

0

DISABLED

1

ENABLED

LOSS OF LOCK MODE

LOL

LD5

LD4

LOCK DETECT CYCLE COUNT

0

0

1024

0

1

2048

1

0

4096

1

1

8192

LD4

LD5

LD

CYCLE

COUNT

0

0

0

0

0

0

0

0

RESERVED

LE1

LE2

LE2

0

1

LE SYNC TO REFERENCE FALLING EDGE

LE SYNC TO REFERENCE RISING EDGE

LE1

0

DISABLED

1

LE SYNCED TO REF IN

LE SYNCHRONIZATION

LE SEL SYNC EDGE

1

Figure 35. Register 7

REGISTER 7

Control Bits

With Bits[C4:C1] set to 0111, Register 7 is programmed. Figure 35

shows the input data format for programming this register.

Reserved

Bits[DB31:DB28] are reserved and must be set to 0. DB26 is

reserved and must be set to 1. DB26 is reserved and must be set

to 1. Bits[DB24:DB10] are reserved and must be set to 0.

LE SEL Sync Edge

Bit DB27 allows selection of the synchronization load enable

(LE) edge to the falling or rising edge of the reference clock,

which is useful for applications that require synchronization to a

common reference edge (see Figure 35). To use this bit, LE sync

(Bit DB25) must be set to 1.

LE Sync

When set to 1, Bit DB25 ensures that the load enable (LE) edge

is synchronized internally with the rising edge of reference

input frequency. This synchronization prevents the rare event of

reference and RF dividers loading at the same time as a falling edge

of the reference frequency, which can lead to longer lock times.

Fractional-N Lock Detect (LD) Cycle Count

LD5 and LD4 (Bits[DB9:DB8]) set the number of consecutive

cycles counted by the lock detect circuitry before asserting lock

detect high (see Figure 35 for details).

Loss of Lock (LOL) Mode

Set the LOL mode bit (Bit DB7) to 1 when the application is a fixed

removed, such as a clocking application. The standard lock detect

be the case with clocking applications. To enable this functionality,

set DB7 to 1.

Fractional-N Lock Detect (LD) Precision

LD3 and LD2 (Bits[DB6:DB5]) set the precision of the lock detect

circuitry in fractional-N mode. LDP is available at 5 ns, 6 ns, 8 ns,

or 12 ns. If bleed currents are used, use 12 ns.

Lock Detect (LD) Mode

t to 0, lock detect precision is set by fractional-N lock detect

precision as described in the Fractional-N Lock Detect (LD)

Precision section. If DB4 is set to 1, lock detect precision is

2.9 ns long, which is more appropriate for integer-N

applications.