ADF4356 datasheet(30/35 Pages) AD

30 / 35 page

ADF4356

Data Sheet

Rev. 0 | Page 30 of 35

FREQUENCY UPDATE SEQUENCE

Frequency updates require updating the auxiliary modulator

(MOD2) in Register 2, the fractional value (FRAC1) in Register 1,

and the integer value (INT) in Register 0. It is recommended to

perform a temperature dependent VTUNE calibration by updating

must be as follows:

1. Register 13.

2. Register 10.

3. Register 2.

4. Register 1.

5. Ensure that >16 ADC_CLK cycles have elapsed between

the write of Register 10 and Register 0. For example, if

ADC_CLK = 99.417 kHz, wait 16/99,417 sec = 161 μs. See the

6. Register 0.

For fPFD > 75 MHz (initially lock with halved fPFD), the sequence

must be as follows:

1. Register 13 (for halved fPFD).

2. Register 10.

3. Register 2 (for halved fPFD).

4. Register 1 (for halved fPFD).

5. Ensure that >16 ADC_CLK cycles have elapsed between

the write of Register 10 and Register 0. For example, if

ADC_CLK = 99.417 kHz, wait 16/99,417 sec = 161 μs. See the

6. Register 0 (for halved fPFD; autocalibration enabled).

7. Register 13 (for the desired fPFD).

8. Register 2 (for the desired fPFD).

9. Register 1 (for the desired fPFD).

10. Register 0 (for desired fPFD; autocalibration disabled).

The frequency change occurs on the write to Register 0.

RF SYNTHESIZER—A WORKED EXAMPLE

Use the following equations to program the ADF4356 synthesizer:

(

)

Divider

MOD1

MOD2

FRAC2

FRAC1

INT

PFD

OUT

(7)

where:

RFOUT is the RF output frequency.

INT is the integer division factor.

FRAC1 is the fractionality.

FRAC2 is the auxiliary fractionality (FRAC2 = (FRAC2_MSB ×

214) + FRAC2_LSB).

MOD2 is the auxiliary modulus (MOD2 = (MOD2_MSB × 214) +

MOD2_LSB).

MOD1 is the fixed 24-bit modulus.

RF Divider is the output divider that divides down the VCO

frequency.

fPFD = REFIN × ((1 + D)/(R × (1 + T)))

(8)

where:

REFIN is the reference frequency input.

D is the REFIN doubler bit.

R is the REFIN reference division factor.

T is the reference divide by 2 bit (0 or 1).

For example, in a universal mobile telecommunication system

(UMTS) where a 2112.8 MHz RF frequency output (RFOUT) is

required, a 122.88 MHz reference frequency input (REFIN)

is available. Note that the ADF4356 VCO operates in the

frequency range of 3400 MHz to 6800 MHz. Therefore, the RF

divider of 2 must be used (VCO frequency = 4225.6 MHz,

RFOUT = VCO frequency/RF divider = 4225.6 MHz/2 =

2112.8 MHz).

The feedback path is also important. In this example, the VCO

output is fed back before the output divider (see Figure 42). In

this example, the 122.88 MHz reference signal is divided by 2 to

generate fPFD of 61.44 MHz. The desired channel spacing is

200 kHz.

PFD

DIVIDER

RFOUT

fPFD

VCO

÷2

Figure 42. Loop Closed Before Output Divider

The worked example is as follows:

N = VCOOUT/fPFD = 4225.6 MHz/61.44 MHz =

68.7760416666666667

INT = int(VCO frequency/fPFD) = 68

FRAC = 0.7760416666666667

MOD1 = 16,777,216

FRAC1 = int(MOD1 × FRAC) = 13,019,818

Remainder = 0.6666666667 or 2/3

MOD2 = fPFD/GCD(fPFD, fCHSP) =

61.44 MHz/GCD(61.44 MHz, 200 kHz) = 1536

FRAC2 = Remainder × 1536 = 1024

From Equation 8,

fPFD = (122.88 MHz × (1 + 0)/2) = 61.44 MHz

(9)

2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +

FRAC2/MOD2)/224))/2

(10)

where:

INT = 68

FRAC1 = 13,019,818

FRAC2 = 1024

MOD2 = 1536

RF Divider = 2

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