ADF4356

Data Sheet

Rev. 0 | Page 28 of 35

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

RESERVED

RESERVED

CONTROL

BITS

0

1

0

0

0

0

0

C3(0) C2(1) C1(1)

C4(1)

0

0

0

0

1

0

0

1

0

0

0

0

0

0

0

0

0

1

0

VH

VH

VCO BAND HOLD

0

1

NORMAL OPERATION

VCO BAND HOLD

Figure 39. Register 11

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

P13

P12

P11

P10

P9

PHASE RESYNC CLOCK VALUE

CONTROL

BITS

P8

P7

P6

P5

P4

P3

P2

P1

0

1

0

1

C3(1) C2(0) C1(0)

C4(1)

P14

P15

P16

P17

P18

P19

P20

P20

P19

...

P5

P4

P3

P2

P1

RESYNC CLOCK

0

0

...

0

0

0

0

0

NOT ALLOWED

0

0

...

0

0

0

0

1

1

0

0

...

0

0

0

1

0

2

.

.

...

.

.

.

.

.

...

0

0

...

1

0

1

1

0

22

0

0

...

1

0

1

1

1

23

0

0

...

1

1

0

0

0

24

.

.

...

.

.

.

.

.

...

1

1

...

1

1

1

0

1

65533

1

1

...

1

1

1

1

0

65534

1

1

...

1

1

1

1

1

1048575

RESERVED

1

1

1

1

Figure 40. Register 12

REGISTER 11

Control Bits

With Bits[C4:C1] set to 1011, Register 11 is programmed. Figure 39

shows the input data format for programming this register.

Reserved

Bits[DB31:DB25] are reserved and must be set to 0. Bit DB22,

Bit DB21, Bit DB16, and Bit DB13 must be set to 1, and all other

bits in this range (Bits[DB23:DB4]) must be set to 0.

VCO Band Hold

VH (Bit DB24), when set to 1, prevents a reset of the VCO core,

band, and bias during a counter reset. VCO band hold is

required for applications that use external PLLs.

REGISTER 12

Control Bits

With Bits[C4:C1] set to 1100, Register 12 is programmed. Figure 40

shows the input data format for programming this register.

Phase Resync Clock Value

P20 to P1 (Bits[DB31:DB12]) set the timeout counter for

activation of phase resync. This value must be set such that

a resync happens immediately after (and not before) the PLL

has achieved lock after reprogramming.

Calculate the timeout value using the following equation:

When not using phase resync, set these bits to 1 for normal

operation.

Reserved

Bits [DB11:DB4] are reserved. Bit DB10 and Bits[DB8:DB4]

must be set to 1, and all other bits in this range must be set to 0.