STM32F031X4 datasheet(20/106 Pages) STMICROELECTRONICS

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Functional overview

STM32F031x4 STM32F031x6

20/106

DocID025743 Rev 4

In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP

capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts

verifications and ALERT protocol management. I2C1 also has a clock domain independent

from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address

match.

The I2C peripheral can be served by the DMA controller.

3.14

Universal synchronous/asynchronous receiver/transmitter

(USART)

The device embeds one universal synchronous/asynchronous receiver/transmitter

(USART1) which communicates at speeds of up to 6 Mbit/s.

It provides hardware management of the CTS, RTS and RS485 DE signals, multiprocessor

communication mode, master synchronous communication and single-wire half-duplex

communication mode. USART1 supports also SmartCard communication (ISO 7816), IrDA

SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and has a clock

domain independent of the CPU clock, allowing to wake up the MCU from Stop mode.

The USART interface can be served by the DMA controller.

Table 6. Comparison of I2C analog and digital filters

Aspect

Analog filter

Digital filter

Pulse width of

suppressed spikes

≥ 50 ns

Programmable length from 1 to 15

I2Cx peripheral clocks

Benefits

Available in Stop mode

–Extra filtering capability vs.

standard requirements

–Stable length

Drawbacks

Variations depending on

temperature, voltage, process

Wakeup from Stop on address

match is not available when digital

filter is enabled.

Table 7. STM32F031x4/x6 I2C implementation

I2C features(1)

1. X = supported.

I2C1

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)

Independent clock

SMBus

Wakeup from STOP

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