DM9102AF datasheet(62/77 Pages) ETC

62 / 77 page

DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

If bit4 = 0, WOL is Active HIGH.

If bit4=1, WOL is Active LOW

If bit6 = 0, WOL is PULSE signal

If bit6=1, WOL is DC LEVEL signal.

Byte Offset (09): New_Capabilities_Enable

Bit0: Directly mapping to bit20 (New Capabilities) of the

PCICS

Byte Offset (14): PMC

Bit7~3: Directly mapping to bit15~11 of PMC (that is

bit31~27 of Power Management Register)

Bit2~0: Directly mapping to bit5~3 of PMC (that is bit21~19

of Power Management Register)

Byte Offset (15):

Bit7~4: Reserved

Bit3: Set to disable the output of PME# pin.

Bit2: Set to disable the output of WOL pin.

Bit1: Set to enable the link change wake up event.

Bit0: Set to enable the Magic packet wake up event.

Byte Offset (16): ID_BLOCK_CRC

This field is implemented to confirm the correct reading of

the EEPROM contents.

2. SROM Version

Current version number is 03.

3. Controller Count

The configuration ROM supports multiple controllers in one

board. Every controller has its unique controller information

block. Controller count indicates the number of controllers

put in the card.

4. Controller_X Information

Each controller has its information block to address its node

ID, GPR control, supported connect media types (Media

Information Block) and other application circuit information

block.

Controller Information Header

ITEM

Offset

Size

Node Address

Controller_x Number

Controller_x Info. Block Offset

5. Controller Information Body Pointed By Controller_X

Info Block Offset Item In Controller Information Header:

Item

Offset

Size

Connection Type Selected

GPR Control

Block Count

Block_1

4+n

* Connect Type Selected indicates the default connect

media type selected.

* GPR Control defines the input or output direction of GPR.

There are three types of block:

1. PHY Information Block (type=01)

2. Media Information Block (type=00)

3. Delay Period Block (type=80)

PHY information Block: (type=01)

Item

Offset

Size

Block Length

Block Type(01)

PHY Number

GPR Initial Length(G_i)

GPR Initial Data

G_i

Reset Sequence Length(R_i)

4+G_i

Reset Data

5+G_i

R_i

Media Capabilities

5+G_i+R_i

Nway Advertisement

7+G_i+R_i

FDX Bit Map

9+G_i+R_i

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