DM9102AF datasheet(48/77 Pages) ETC

номер детали	DM9102AF

подробное описание детали	Single Chip Fast Ethernet NIC controller

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производитель	ETC [List of Unclassifed Manufacturers]

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DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

b3 b2 b1 b0

In IDLE state

Ability match

Acknowledge match

Acknowledge match fail

Consistency match

Consistency match fail

Parallel detects signal_link_ready

fail

Auto-negotiation completed

successfully

10BASE-T Configuration/Status (10BTCSRCSR) - 12h

Bit

Name

Default

Description

18.15

Reserved

0, RO

Reserved:

Write as 0, ignore on read

18.14

LP_EN

1, RW

Link Pulse Enable:

1=Transmission of link pulses enabled

0=Link pulses disabled, good link condition forced

This bit is valid only in 10Mbps operation.

18.13

HBE

1,RW

Heartbeat Enable:

1=Heartbeat function enabled

0=Heartbeat function disabled

When the DM9102A is configured for Full Duplex operation, this bit will be

ignored (the collision/heartbeat function is invalid in Full Duplex mode). It must

set to be 1.

18.12

SQUELCH

1, RW

Squelch Enable

1 = normal squelch

0 = low squelch

18.11

JABEN

1, RW

Jabber Enable:

Enables or disables the Jabber function when the DM9102A is in 10BASE-T

Full Duplex or 10BASE-T Transceiver Loopback mode

1= Jabber function enabled

0= Jabber function disabled

18.10-18.0

Reserved

0, RO

Reserved

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