DM9102AF datasheet(35/77 Pages) ETC

35 / 77 page

DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

CRDOUT

1,RW

Data_Out from EEPROM

This bit is set to reflect the signal status of EEDI pin when EEPROM mode is

selected.

CRDIN

1,RW

Data_In to EEPROM

This bit is set to generate the output signal to EEDO pin when EEPROM mode is

selected.

CRCLK

1,RW

Clock to EEPROM

This bit is set to generate the output clock to EECLK pin when EEPROM mode is

selected.

CRCS

1,RW

Chip_Select to EEPROM

This bit is set to generate the output signal to EECS pin when EEPROM mode is

selected.

11. Programming ROM Address Register (CR10)

29 28 27 26 25 24 23 22 21 20 19 18

13 12

11 10

Bit

Name

Default

Description

17:0

BADR

Unpredictable

Boot ROM Address

This field contains the address pointer for Boot ROM when the mode of

programming by register is selected.

12. General Purpose Timer Register (CR11)

29 28 27 26 25 24 23 22 21 20 19 18

13 12

11 10

Bit

Name

Default

Description

TCON

0,RW

Continuous Mode of Timer

When this bit is set, the timer will continuously re-initiated upon the set time is up.

When reset, the timer will be one-shot response after BCLK value is programmed.

15:0

MBCLK

0000h,RW

Multiple of Base Clock

This field set the iteration number of base clock. The base clock duration is defined

to be

81.92us --- for MII port/100M is selected

2us --- for MII port/10M is selected

13. PHY Status Register (CR12)

29 28 27 26 25 24 23 22 21 20 19 18

13 12

11 10

Bit

Name

Default

Description

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