DM9102AF datasheet(41/77 Pages) ETC

номер детали	DM9102AF

подробное описание детали	Single Chip Fast Ethernet NIC controller

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DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

PHY Management Registers

Offset

Description

Default value after reset

BMCR

Basic Mode Control Register

3100h

BMSR

Basic Mode Status Register

7809h

PHYIDR1

PHY Identifier Register #1

0181h

PHYIDR2

PHY Identifier Register #2

B840h

ANAR

Auto-Negotiation Advertisement Register

01E1h

ANLPAR

Auto-Negotiation Link Partner Ability Register

0000h

ANER

Auto-Negotiation Expansion Register

0000h

7-15

Reserved

0000h

10h

DSCR

DAVICOM Specified Configuration Register

0000h

11h

DSCSR

DAVICOM Specified Configuration/Status Register

F010h

12h

10BTCSR

10BASE-T Configuration/Status Register

7800h

Others

Reserved

Reserved for future use, do not Read/Write to these

Registers

0000h

Key to Default

In the register description that follows, the default column

takes the form:

Where

<Reset Value>:

Bit set to logic one

Bit set to logic zero

No default value

(PIN#)

Value latched in from pin # at reset

<Access Type>:

RO = Read only

RW = Read/Write

<Attribute (s)>:

SC = Self clearing

P = Value permanently set

LL = Latching low

LH = Latching high

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