DM9102AF datasheet(40/77 Pages) ETC

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DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

General Wake-up

Event

This bit reflects the current state of the wake-up event. It is cleared when either the

General Wake-up Event in the Function Event Register is cleared or when the

PME_Status in the PMC is cleared.

This bit is cleared upon hardware or software reset.

5:14

Reserved

R/W

Unpredictable on read

Interrupt

This bit reflects the internal state of a function specific interrupt. It is cleared when

the event that caused the interrupt was either masked in CSR7, or cleared in

CSR5.

This bit is cleared upon hardware or software reset.

16:31

Reserved

R/W

Unpredictable on read

4. Function Force Event Register: (offset 8Ch)

Bit

Name

Default

Description

0:3

Reserved

R/W

Unpredictable on read

Force Wake-up

Writing 1 to this bit sets the wake-up event field in the Function Event Register

(Function Event Register<4>), but not in the Function Present State Register

(Function Present State Register<4>).

Writing 0 has no effect.

5:14

Reserved

R/W

Unpredictable on read

Force Interrupt

Writing 1 to this bit sets the interrupt field in the Function Event Register (Function

Event Register<15>), but not in the Function Present State Register (Function

Present State Register<15>).

Writing 0 has no effect.

16:31

Reserved

R/W

Unpredictable on read

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