DM9102AF datasheet(32/77 Pages) ETC

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DM9102A

Single Chip Fast Ethernet NIC controller

Final

Version: DM9102A-DS-F03

August 28, 2000

PBF

0,RW

Pass Bad Frame

When set, the DM9102 is indicated to receive the bad frames including runt

packets, truncated frames caused by the FIFO overflow. The bad frame also has to

pass the address filtering if the DM9102A is not set in promiscuous mode.

HOFM

0,RO

Hash-only Filter Mode

This is a read-only bit and mapped from the set-up frame together with bit4,0 of

CR6.

It is set to indicate the DM9102A operate in a Hash-only Filtering Mode.

RXRC

0,RW

Receive Start/Stop Command

When set, receive process will begin by fetching the receive descriptor for available

buffer to store the new-coming packet (placed in the running state). If the fetched

descriptor is owned by the host (no descriptor is owned by the DM9102A), the

receive process will enter the suspend state and receive buffer unavailable

CR5<7> sets. Otherwise it runs to wait for the packet’s income. When reset,

receive process is placed in the stopped state after completing the reception of the

current frame.

HPFM

0,RO

Hash/Perfect Filter Mode

This is a read only bit and mapped from the setup frame together with CR6<4>,

CR6<2>. When reset, the DM9102A does a perfect address filter of incoming

frames according to the addresses specified in the setup frame. When set, the

DM9102A does a imperfect address filtering for the incoming frame with a multicast

address according to the hash table specified in the setup frame. The filtering mode

(perfect / imperfect) for the frame with a physical address will depend on CR6<2>.

8. Interrupt Mask Register (CR7)

987

Bit

Name

Default

Description

NISE

0,RW

Normal Interrupt Summary Enable

This bit is set to enable the interrupt for Normal Interrupt Summary.

Normal interrupt includes three conditions :

CR5<0> – TXCI : Transmit Complete Interrupt

CR5<2> – TXDU : Transmit Buffer Unavailable

CR5<6> – RXCI : Receive Complete Interrupt

AISE

0,RW

Abnormal Interrupt Summary Enable

This bit is set to enable the interrupt for Abnormal Interrupt Summary.

Abnormal interrupt includes all interrupt condition as shown below excluding

Normal Interrupt conditions. They are TXPS(bit1), TXJT(bit3), TXFU(bit5),

RXDU(bit7), RXPS(bit8), RXWT(bit9), TXER(bit10), GPT(bit11), SBE(bit13).

ERIE

0,RW

Early Receive Interrupt Enable

This bit is set to enable the interrupt for Early Receive.

SBEE

0,RW

System Bus Error Enable

When set together with CR7<15>, CR5<13>, it enables the interrupt for System

Bus Error. The type of system bus error is shown in CR5<24:23>.

LCIE

0,RW

Link Status Change Interrupt Enable

This bit is set to enable the interrupt for link status change.

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