XRT8001IP datasheet(40/48 Pages) EXAR

40 / 48 page

XRT8001

Rev. 1.01

In this case, the user must set the “E1/T1* SELECT”

signal to “HIGH”, order to select “E1 rates” (2.048MHz).

By doing this, the 2.048MHz clock signal (from the T1/

E1 LIU) is selected and will be applied to the “FIN” input

of the XRT8001, and the XRT8001 will configured to

operate in the “Master” Mode.

At this point, the user will need to execute the appro-

priate steps in order to configure the XRT8001 into the

1.544MHz

74AHCT193

LOAD

CLR

Load-in-64

E1/T1* SELECT

XRT8001

FIN

SCLK

SDO

SDI

MSB

CLK1

CLK2

LOCKDET

+5V

U5A

74AHCT04

LOCK_DET

1.544MHz

74AHCT157

A/B

8001_SDO

74AHCT193

LOAD

CLR

1.544MHz or 2.048MHz

Divide-by-193

8kHz or 2.048MHz

8001_SDI

8001_CS

E1/T1* SELECT

1.544MHz or 2.048MHz

8001_SCLK

“E1 to T1 Forward/Master” Mode.

9.1 Hardware and Software Implementation Details

Figure x presents a simple block diagram of a design

that can accept either a 1.544MHz or a 2.048MHz

clock signal, and synthesize a 1.544MHz clock signal.

Now we need to provide some details. Hence, Figure

24 presents a circuit schematic which realizes the

function, depicted in Figure 23.

Next, we describe how to configure the circuitry in

Figure 24 to accept a 2.048MHz clock signal, and

configure it to synthesize a 1.544MHz clock signal by

executing five steps. We also describe how to accept

a 1.544MHz clock signal and configure it to synthesize

a 1.544MHz clock.

9.2 Configuring the Circuitry in Figure 6 to accept

a 2.048MHz clock in order to synthesize a 1.544MHz

output clock.

STEP 1 – Drive the “E1/T1* SELECT” input pin to

“HIGH”. This step configures the “2:1 MUX” to select

and apply the 2.048MHz clock to the “FIN” input of the

XRT8001 WAN Clock, as well as configuring the

XRT8001 WAN Clock into the “Master Mode”.

NOTE: The next steps are devoted to configuring the

XRT8001 WAN Clock into the “E1 to T1 Forward/Master”

Mode.

STEP 2 – Write the binary value “1000” into Command

indicated below.

Command Register, CR0 (Address = 0x00)

IOC4

IOC3

IOC2

IOC1

PL1EN

Figure 24: Hardware Design Implementation of Figure 23.

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