XRT8001IP datasheet(28/48 Pages) EXAR

28 / 48 page

XRT8001

Rev. 1.01

For example, if the user wishes to input a clock signal

of 2.048MHz, to the “FIN” input pin (e.g., where Q = 1),

then he/she should write a “0” into Command Register

CR1.

Note: If the user wishes to output a clock signal via the

CLK2 output signal, then he/she should also write a “1” into

the “PL2EN” bit-field within Command Register CR1.

Step 4 – Write the binary expression “11111” into

Command Register CR2, as illustrated below.

This step is necessary in order to insure proper opera-

tion of the XRT8001.

Command Register, CR2 (Address = 0x02)

SEL14

SEL13

SEL12

SEL11

SEL10

Step 5 – Write the binary expression “11111” into

Command Register CR3, as illustrated below.

This step is necessary in order to insure proper opera-

tion of the XRT8001. This step is also illustrated

below.

Command Register, CR3 (Address = 0x03)

SEL24

SEL23

SEL22

SEL21

SEL20

Step 6 – Enable any of the following output signals as

appropriate:

“SYNC”, “CLK1”, “CLK2” and

“LOCKDET”.

This is accomplished by writing a “1” into the corre-

sponding bit-fields, within Command Register CR4, as

illustrated below.

Command Register CR4, (Address = 0x04)

SYNCEN

CLK1EN

CLK2EN

LDETDIS2

LDETDIS1

6.6 The “High Speed – Reverse” Mode

When the XRT8001 WAN Clock has been configured to

operate in the “High Speed – Reverse” Modes, its

operation is independent of whether it has been config-

ured in the "Master" or "Slave" Mode.

When the XRT8001 WAN Clock has been configured to

operate in the “High Speed – Reverse” Modes, then it

will accept a “64kHz” clock signal via the “Reference

Clock” input at FIN (pin 3). In response, to this clock

signal, the XRT8001 WAN Clock will output an “M x

2.048MHz” clock signal via the Clock Output pins

(CLK1 and/or CLK2); where M can only have the values

1, 2,4 or 8.

A simple illustration of the XRT8001 WAN Clock,

operating in the “High Speed – Reverse” Mode is

presented in Figure 17.

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