XRT8001IP datasheet(32/48 Pages) EXAR

32 / 48 page

XRT8001

Rev. 1.01

1.544 MHz or

2.048 MHz

1.544 MHz or

2.048 MHz

CLK1

CLK2

8 kHz

FIN

Figure 19. XRT8001 Reverse/Slave Mode

6.10 Phase relationship between the “FIN” input

and the “CLK1 and CLK2” outputs

The Phase relationship depends upon whether the

XRT8001 is operating in the “Slave” or “Master” Mode.

6.11 Slave Mode:

If the XRT8001 is operating in the “Slave” Mode, then

there is a specific phase relationship between the “FIN”

and the “CLK1, CLK2” outputs. The reasons are as

follows.

For Slave Mode Operation, the XRT8001 accepts a

8kHz clock signal (which it will also synthesize and

output via the SYNC output signal). Each of the two

PLLs (within the XRT8001) will be configured to gener-

ate either a “K x 56kHz” or a “K x 64kHz” clock signal.

Hence, in the “Slave Mode”, the “SYNC” output, is

simply a buffered version of the “FIN” input. Therefore,

generate a “K x 56kHz” clock signal.

the “SYNC” signal is approximately 4ns delayed from

the “FIN” input signal.

Each of the two PLLs “lock” onto the “SYNC” signal, for

frequency synthesis.

This timing relationship (between FIN and the CLK1,

CLK2 signals) depends upon the “CLK1” and “CLK2”

signal frequencies and as listed in the following tables.

NOTES:

Table 9 presents the timing relationship between the

“FIN” and the “CLK1, CLK2” if the PLLs are configured

generate a “K x 64kHz” clock signal.

Table 10 presents the timing relationship between the

“FIN” and the “CLK1, CLK2” if the PLLs are configured to

generate a “K x 56kHz” clock signal.

FIN

CLK2

CLK1

Figure 20: Timing Relationship between the FIN and the “CLK1/CLK2” outputs

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