XRT8001IP datasheet(34/48 Pages) EXAR

34 / 48 page

XRT8001

Rev. 1.01

Values written into

Value for K

CLK1/CLK2

T (ns)

“SEL1[4:0]

(K x 56kHz)

Output Frequency

00000

56kHz

376

00001

112kHz

376

00010

168kHz

376

00011

224kHz

376

00100

280kHz

450

00101

336kHz

376

00110

392kHz

323

00111

448kHz

283

01000

504kHz

500

01001

560kHz

450

01010

616kHz

410

01011

672kHz

376

01100

728kHz

347

01101

784kHz

323

01110

840kHz

302

01111

896kHz

283

10000

952kHz

529

10001

1.008MHz

500

10010

1.064MHz

474

10011

1.120MHz

450

10100

1.176MHz

429

10101

1.232MHz

410

10110

1.288MHz

392

10111

1.344MHz

376

11000

1.400MHz

361

11001

1.456MHz

347

11010

1.512MHz

335

11011

1.568MHz

323

11100

1.624MHz

312

11101

1.680MHz

302

11110

1.756MHz

292

11111

1.812MHz

283

Table 10: Timing Relationship (T), from the rising edge of “CLK1/CLK2” to the rising edge of “FIN”

with the XRT8001 in Slave Mode, and FIN = 8kHz

6.12 Master Mode:

If the XRT8001 is operating in the “Master” Mode, then

the timing relationship between the “Reference signal”

(e.g., a signal applied to the “FIN” and the “CLK1” or

“CLK2” output is not readily available. This is because

the “FIN” signal is internally divided down, via a

Programmable Divider, which generates the “SYNC”

signal. The internal Phase Locked Loops (within the

XRT8001) are “locked” onto the “SYNC” signal. Hence,

there is definitely a phase relationship between the

“SYNC” and the “CLK1, CLK2” outputs.

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