XRT8001IP datasheet(24/48 Pages) EXAR

24 / 48 page

XRT8001

Rev. 1.01

Input

Frequency

PLL1 Output

Frequency

PLL2 Output

Frequency

Value to Write to

D4 – D1 in CR0

56kHz

1.544MHz

2.048MHz

0011

64kHz

1.544MHz

2.048MHz

0111

Table 5. Listing of “Input Frequency” and “Output Frequency”

Cases for “Reverse/Master” Mode Operation

Step 3 – Upon reviewing Table 5, write the listed value

(under the “Value to Write to D4 – D1 in CR0” register)

into the D4 through D1 bit-fields within Command

Command Register CR0 (Address = 0x00)

IOC4

IOC3

IOC2

IOC1

PL1EN

Value to Write to D4 – D1 in CR0

Note:

If the user wishes to output a clock signal via the

CLK1 output signal, then he/she should also write a “1” into

the “PL1EN” bit-field within Command Register CR0.

This step configures the XRT8001 to operate in the

“Reverse/Master” Mode.

Step 4 – Write a “1” into the “PL2EN” bit-field within

Command Register CR1 (if you wish to output a clock

signal via the “CLK2” output pin), as illustrated below:

Command Register, CR1 (Address = 0x01)

PL2EN

Don’t Care

Notes:

1. The value of the “D4 through D1” bit-fields within

Command Register, CR1 are “Don’t Care”.

2. The contents of Command Registers CR2 and

CR3 are “Don’t Care”.

Step 5 – Enable any of the following output signals as

appropriate: SYNC”, CLK1, CLK2 and LOCKDET.

This is accomplished by writing a “1” into the corre-

sponding bit-fields, within Command Register CR4, as

illustrated below:

Command Register CR4, (Address = 0x04)

SYNCEN

CLK1EN

CLK2EN

LDETDIS2

LDETDIS1

Note: For information on the “LDETDIS1” and “LDETDIS2”

bit-fields, please see Table 3.

6.2 The “Fractional T1/E1 Reverse/Master” Mode

When the XRT8001 WAN Clock has been configured to

operate in the “Fractional T1/E1 Reverse/Master"

Mode, then it will accept either a “P x 56kHz” or a “P x

64kHz” clock signal via the “FIN” input pin (pin 3). In

response, the XRT8001 will output either a 1.544MHz

or a 2.048MHz clock signal via the CLK1 and/or CLK2

outputs.

A simple illustration of the XRT8001 WAN Clock,

operating in the “Fractional T1/E1 Reverse/Master”

Mode is presented in Figure 15.

XRT8001IP датащи(PDF) 24 Page - Exar Corporation

XRT8001IP датащи(HTML) 24 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL