VDP3133Y datasheet(30/76 Pages) MICRONAS

30 / 76 page

VDP 313xY

ADVANCE INFORMATION

Micronas

2.14.2.Control and Status Registers

Table 2–4 gives definitions of the VDP control and sta-

tus registers. The number of bits indicated for each

in hardware, i.e. a 9-bit register must always be

accessed using two data bytes but the 7 MSB will be

‘don’t care’ on write operations and ‘0’ on read opera-

tions. Write registers that can be read back are indi-

cated in Table 2–4.

Functions implemented by software in the on-chip con-

trol microprocessor (FP) are explained in Table 2–6.

A hardware reset initializes all control registers to 0.

The automatic chip initialization loads a selected set of

registers with the default values given in Table 2–4.

The register modes given in Table 2–4 are

– w: write only register

– w/r:write/read data register

– r:

read data from VPC

– v:

– h: register is latched with horizontal sync

Table 2–4: I2C control and status registers of the video frontend

I2C Sub

address

Number

of bits

Mode

Function

Default

Name

(hex)

FP Interface

FP status

bit[0]

write request

bit[1]

read request

bit[2]

busy

FPSTA

bit[8:0]

9-bit FP read address

bit[11:9]

reserved, set to zero

FPRD

bit[8:0]

9-bit FP write address

bit[11:9]

reserved, set to zero

FPWR

w/r

bit[11:0]

FP data register,

reading/writing to this register will

autoincrement the FP read/write

address.

Only 16 bit of data are transferred

per I2C teleramm.

FPDAT

Black Line Detector

read only register, do not write to this register!

after reading, LOWLIN and UPLIN are reset to 127 to

start a new measurement

bit[6:0]

number of lower black lines

bit[7]

always 0

bit[14:8]

number of upper black lines

bit[15]

normal/black picture

−

BLKLIN

LOWLIN

UPLIN

BLKPIC

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