VDP3133Y datasheet(29/76 Pages) MICRONAS

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ADVANCE INFORMATION

VDP 313xY

Micronas

2.14.Serial Interface

2.14.1.I2C-Bus Interface

Communication between the VDP and the external

controller is done via I2C-bus. The VDP has two

I2C-bus slave interfaces (for compatibility with VPC/

DDP applications) - one in the front-end and one in the

back-end. Both I2C-bus interfaces use I2C clock syn-

chronization to slow down the interface if required.

Both I2C-bus interfaces use one level of subaddress:

the I2C-bus chip address is used to address the IC and

a subaddress selects one of the internal registers. The

I2C-bus chip addresses are given below:

The registers of the VDP have 8 or 16-bit data size;

16-bit registers are accessed by reading/writing two

8-bit data words.

Fig. 2–27 shows I2C-bus protocols for read and write

operations of the interface; the read operation requires

an extra start condition and repetition of the chip

address with read command set.

Fig. 2–27: I2C-bus protocols

Table 2–3: I2C Chip Addresses

Chip

Address

R/W

front-end

001

111/0

back-end

001

011/0

SDA

SCL

1000 111

WAck

Ack

0111 1100

Ack

1 or 2 byte Data

1000 111

high byte Data

low byte Data

Ack

Nak

Start

Stop

Ack

Nak P

I2C write access

subaddress 7c

I2C read access

subaddress 7c

Ack

1000 111

W Ack

FPWR

Ack

byte high

send FP-address-

Ack

byte low

send FP-address-

Ack

1000 111

W Ack

FPDAT

Ack

byte high

send data-

Ack

byte low

send data-

Ack

I2C write access

to FP

1000 111

W Ack

FPRD

Ack

byte high

send FP-address-

Ack

byte low

send FP-address-

Ack

1000 111

W Ack

FPDAT

Ack

byte high

receive data-

Ack

byte low

receive data-

Nak

I2C read access

to FP

1000 111

R Ack

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