VDP3133Y datasheet(37/76 Pages) MICRONAS

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ADVANCE INFORMATION

VDP 313xY

Micronas

measurement adc status and fast blank input status

measurement status register

bit[0]

0/1

tube measurement active /

complete

bit[2:1]

white drive measurement cycle

red

green

blue

reserved

bit[3]

0/1

picture measurement active /

complete

bit[4]

0/1

fast blank input low / high (static)

bit[5]

fast blank input negative transi-

tion since last read (bit reset at

read)

bit[7:6]

reserved

−

PMS

Vertical Timing

w v

vertical blanking start

bit[8:0]

0..511

first line of vertical blanking

305

VBST

w v

vertical blanking stop

bit[8:0]

0..511

last line of vertical blanking

VBSO

w v

free running field period

bit[8:0]

period = (value+4) lines

309

VPER

Horizontal Deflection and Timing

w v

linear term of angle & bow correction

bit[8:0]

−256..+255 ± 500 ns

0ANGLE

w v

quadratic term of angle & bow correction

bit[8:0]

−256..+255 ± 500 ns

0BOW

w v

adjustable delay of PLL2, clamping, and blanking

(relative to front sync)

bit[8:0]

−256..+255 ± 8 µs

−141

POFS2

w v

adjustable delay of horizontal drive & flyback (relative

to PLL2)

bit[8:0]

−256..+255 ± 8 µs

0POFS3

w v

adjustable delay of main sync (relative to PLL2)

adjust horizontal position for digital picture

bit[8:0]

20 steps=1

µs

120

HPOS

w v

start of horizontal blanking

bit[8:0]

0..511

HBST

w v

end of horizontal blanking

bit[8:0]

0..511

HBSO

Table 2–5: I2C control and status registers of the video backend

(Registers are set to ’0’ at reset, default values are recommendations)

I2C Sub

address

Number

of bits

Mode

Function

Default

Name

(hex)

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