VDP3133Y datasheet(56/76 Pages) MICRONAS

56 / 76 page

VDP 313xY

ADVANCE INFORMATION

Micronas

Pin 37, 38, 39

− Analog RGB Outputs, ROUT, GOUT,

BOUT (Fig. 3–12)

This are the analog Red/Green/Blue outputs of the

backend. The outputs sink a current of max. 8 mA.

Pin 40

− DAC Reference Decoupling, VRD (Fig. 3–20)

Via this pin the DAC reference voltage is decoupled by

an external capacitance. The DAC output currents

depend on this voltage, therefore a pull-down transis-

tor can be used to shut off all beam currents. A decou-

pling capacitor of 3.3

µF/100 nF is required.

Pin 41, 42, 43, 45, 46, 47

− Analog RGB Inputs, RIN1/

2, GIN1/2, BIN1/2 (Fig. 3–11)

These pins are used to insert an external analog RGB

signal, e.g. from a SCART connector which can by

switched to the analog RGB outputs with the fast blank

signal. The analog backend provides separate bright-

ness and contrast settings for the external analog RGB

signals.

Pin 44, 48

− Fast Blank Inputs, FBLIN1/2 (Fig. 3–15)

These pins are used to switch the RGB outputs to the

external analog RGB inputs.

Pin 49

− Main Clock Output, CLK20 ( Fig. 3–6)

This is the 20.25 MHz main system clock, that is used

by all circuits in a high-end VDP system. All external

timing is derived from this clock.

Pin 50

− Horizontal Drive Output, HOUT (Fig. 3–13)

This open drain output supplies the the drive pulse for

the horizontal output stage. The polarity and gating

with the flyback pulse are selectable by software.

Pin 51, 52

− Crystal Input and Output, XTAL1, XTAL2

(Fig. 3–5)

These pins are connected to an 20.25 MHz crystal

oscillator is digitally tuned by integrated shunt capaci-

tances. The Clk20 signal is derived from this oscillator.

Pin 53, 54, 60

− Analog Chroma Inputs, CIN1, CIN2/

CRIN, CBIN, (Fig. 3–7, Fig. 3–8)

CIN1, CIN2 are the analog chroma inputs for S-VHS. A

S-VHS chroma signal is converted using the chroma

(Video2) AD converter. A resistive devider is used to

BIAS the inout signal to middle of converter range. The

input signal must be AC coupled. Together with the

CBIN pin CIN2 can alternatively be used as chroma

component input for the analog YCRCB interface.

Pin 55

− Ground (Analog Front-end), GNDAF

Pin 56

− Ground (Analog Signal Input),

SGND (Fig. 3–10)

This is the high quality ground reference for the video

input signals.

Pin 57

− Reference Voltage Top, VRT (Fig. 3–10)

Via this pin, the reference voltage for the A/D convert-

ers is decoupled. The pin is connected with 10

µF/

47 nF to the Signal Ground Pin.

Pin 58

− Supply Voltage (Analog Front-end), VSUPAF

Pin 59

− Analog Video Output, VOUT (Fig. 3–9)

The analog video signal that is selected for the main

(luma, cvbs) adc is output at this pin. An emitter fol-

lower is required at this pin.

Pin 61...64

− Analog Video Input 1−4, VIN1−4 (Fig. 3–

These are the analog video inputs. A CVBS or S-VHS

luma signal is converted using the luma (Video 1) AD

converter. The input signal must be AC-coupled.

3.4. Pin Configuration

Fig. 3–2: 64-pin PSDIP package

TEST

RESQ

SCL

SDA

GNDD

HCS

FSY

CSY

INTLC

VPROT

SAFETY

HFLB

GNDD

VSUPD

GNDD

VIN4

VIN3

VIN2

VIN1

CIN1

VOUT

VSUPAF

VRT

SGND

GNDAF

CBIN

CIN 2/CRIN

XTAL 2

XTAL 1

HOUT

CLK20

VSUPD

GNDD

RSW2

FBLIN2

BIN2

GIN2

RIN2

FBLIN

BIN

GIN

RIN

VRD

BOUT

RSW1

SENSE

GNDM

VERTQ

VERT

E/W

GOUT

ROUT

VSUPAB

GNDAB

SVMOUT

XREF

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