MCP3913 datasheet(66/82 Pages) MICROCHIP

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MCP3913

DS20005227A-page 66

 2013 Microchip Technology Inc.

8.7

CONFIG0 Register –

Configuration Register 0

Name

Bits

Address

Cof.

CONFIG0

0x0D

R/W

CONFIG0 REGISTER

R/W-0

R/W-1

R/W-0

EN_OFFCAL

EN_GAINCAL

DITHER<1>

DITHER<0>

BOOST<1>

BOOST<0>

PRE<1>

PRE<0>

bit 23

bit 16

R/W-0

R/W-1

U-0

OSR<2>

OSR<1>

OSR<0>

—

bit 15

bit 8

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

VREFCAL<7>

VREFCAL<6>

VREFCAL<5>

VREFCAL<4>

VREFCAL<3>

VREFCAL<2>

VREFCAL<1>

VREFCAL<0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 23

EN_OFFCAL:

Enables the 24-bit digital offset error calibration on all channels

= Enabled. This mode does not add any group delay to the ADC data.

= Disabled (DEFAULT)

bit 22

EN_GAINCAL:

Enables or disables the 24-bit digital gain error calibration on all channels

= Enabled. This mode adds a group delay on all channels of 24 DMCLK periods. All data ready

pulses are delayed by 24 DMCLK clock periods, compared to the mode with EN_GAINCAL = 0.

= Disabled (DEFAULT)

bit 21-20

DITHER<1:0>:

Control for dithering circuit for idle tone’s cancellation and improved THD on all channels

= Dithering ON, Strength = Maximum (DEFAULT)

= Dithering ON, Strength = Medium

= Dithering ON, Strength = Minimum

= Dithering turned OFF

bit 19-18

BOOST<1:0>:

Bias Current Selection for all ADCs (impacts achievable maximum sampling speed, see

Table 5-2)

= All channels have current x 2

= All channels have current x 1 (Default)

= All channels have current x 0.66

= All channels have current x 0.5

bit 17-16

PRE<1:0>

Analog Master Clock (AMCLK) Prescaler Value

= AMCLK = MCLK/8

= AMCLK = MCLK/4

= AMCLK = MCLK/2

= AMCLK = MCLK (Default)

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