MCP3913 datasheet(37/82 Pages) MICROCHIP

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 2013 Microchip Technology Inc.

DS20005227A-page 37

MCP3913

The two PHASE0/1 registers are split into three 12-bit

banks that represent the delay between each pair of

channels. The equivalence is defined in Table 5-8.

Each phase value (PHASEA/B/C) represents the delay

of the even channel with respect to the associated odd

channel with an 11-bit plus sign, MSB-first two's

complement code. This code indicates how many

DMCLK periods there are between each channel in the

pair. (see Equation 5-5). Since the odd channels are

the time reference, when PHASEX<11:0> is positive,

the even channel of the pair is lagging and the odd

channel is leading. When PHASEX<11:0> is negative,

the even channel of the pair is leading and the odd

channel is lagging.

EQUATION 5-5:

The timing resolution of the phase delay is 1/DMCLK or

1 µs in the default configuration with MCLK = 4 MHz.

Given the definition of DMCLK, the phase delay is

affected by a change in the prescaler settings

(PRE<1:0>) and the MCLK frequency.

The data ready signals are affected by the phase delay

settings. Typically, the time difference between the data

ready pulses of odd and even channels is equal to the

associated phase delay setting.

Each ADC conversion start and, therefore, each data

ready pulse is delayed by a timing of OSR/2 x DMCLK

periods (equal to half a DRCLK period). This timing

allows for the odd channel’s data ready signals to be

located at a fixed time reference (OSR/2 x DMCLK

periods from the reset), while the even channel can be

leading or lagging around this time reference with the

corresponding PHASEX<11:0> delay value.

5.9.1

PHASE DELAY LIMITS

The limits of the phase delays are determined by the

OSR settings: the phase delays can only go from

-OSR/2 to +OSR/2-1 DMCLK periods.

If larger delays between the two channels are needed,

they can be implemented externally to the chip with an

MCU. A FIFO in the MCU can save incoming data from

the leading channel for a number N of DRCLK clocks.

In this case, DRCLK would represent the coarse timing

resolution, and DMCLK the fine timing resolution. The

total delay will then be equal to:

EQUATION 5-6:

The Phase delay registers can be programmed once

with the OSR = 4096 setting, and will adjust the OSR

automatically afterwards without the need to change

the value of the phase registers.

• OSR = 4096

: The delay can go from -2048 to

+2047. PHASEX<11> is the sign bit.

PHASEX<10> is the MSB and PHASEX<0> the

LSB.

• OSR = 2048

: The delay can go from -1024 to

+1023. PHASEX<10> is the sign bit. PHASEX<9>

is the MSB and PHASEX<0> the LSB.

• OSR = 1024

: The delay can go from -512 to +511.

PHASEX<9> is the sign bit. PHASEX<8> is the

MSB and PHASEX<0> the LSB.

•OSR = 512

: The delay can go from -256 to +255

PHASEX<8> is the sign bit. PHASEX<7> is the

MSB and PHASEX<0> the LSB.

• OSR = 256: The delay can go from -128 to +127.

PHASEX<7> is the sign bit. PHASEX<6> is the

MSB and PHASEX<0> the LSB.

• OSR = 128: The delay can go from -64 to +63.

PHASEX<6> is the sign bit. PHASEX<5> is the

MSB and PHASEX<0> the LSB.

• OSR = 64: The delay can go from -32 to +31.

PHASEX<5> is the sign bit. PHASEX<4> is the

MSB and PHASEX<0> the LSB.

• OSR = 32: The delay can go from -16 to +15.

PHASEX<4> is the sign bit. PHASEX<3> is the

MSB and PHASEX<0> the LSB.

TABLE 5-8:

PHASE DELAYS

EQUIVALENCE

Pair of

channels

Phase Bank

Position

CH1/CH0

PHASEA<11:0>

PHASE1<11:0>

CH3/CH2

PHASEB<11:0>

PHASE1<23:12>

CH5/CH4

PHASEC<11:0>

PHASE0<11:0>

Note:

For a detailed explanation of the data

ready pin (DR) with phase delay, see

Figure 5.11.

Total Delay

PHASEX<11:0> Decimal Code

DMCLK

-----------------------------------------------------------------------------------

where: X = A/B/C

Note:

Rewriting the PHASE registers with the

same value automatically resets and

restarts all ADCs.

Total Delay = N/DRCLK + PHASE/DMCLK

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