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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MCP3913 датащи(PDF) 61 Page - Microchip Technology |
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MCP3913 датащи(HTML) 61 Page - Microchip Technology |
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61 / 82 page  2013 Microchip Technology Inc. DS20005227A-page 61 MCP3913 8.3 PHASE0 Register – Phase Configuration Register for Channel Pair 4/5 Any write to this register automatically resets and restarts all active ADCs. Name Bits Address Cof. PHASE0 24 0x09 R/W REGISTER 8-3: PHASE0 REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 —— — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — PHASEC<11> PHASEC<10> PHASEC<9> PHASEC<8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEC<7> PHASEC<6> PHASEC<5> PHASEC<4> PHASEC<3> PHASEC<2> PHASEC<1> PHASEC<0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-12 Unimplemented: Read as 0 bit 11-0 PHASEC<11:0> Phase delay between channels CH4 and CH5 (reference). Delay = PHASEC<11:0> decimal code/DMCLK |
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