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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MCP3913 датащи(PDF) 57 Page - Microchip Technology |
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MCP3913 датащи(HTML) 57 Page - Microchip Technology |
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57 / 82 page  2013 Microchip Technology Inc. DS20005227A-page 57 MCP3913 8.0 MCP3913 INTERNAL REGISTERS The addresses associated with the internal registers are listed in Table 8-1. This section also describes the registers in detail. All registers are 24-bit long registers, which can be addressed and read separately. The format of the data registers (0x00 to 0x05) can be changed with WIDTH_DATA<1:0> bits in the STATUSCOM register. The READ<1:0> and WRITE bits define the groups and types of registers for continuous read/write communication or looping on address sets, as shown in Table 8-2. TABLE 8-1: MCP3913 REGISTER MAP Address Name Bits R/W Description 0x00 CHANNEL0 24 R Channel 0 ADC Data <23:0>, MSB first 0x01 CHANNEL1 24 R Channel 1 ADC Data <23:0>, MSB first 0x02 CHANNEL2 24 R Channel 2 ADC Data <23:0>, MSB first 0x03 CHANNEL3 24 R Channel 3 ADC Data <23:0>, MSB first 0x04 CHANNEL4 24 R Channel 4 ADC Data <23:0>, MSB first 0x05 CHANNEL5 24 R Channel 5 ADC Data <23:0>, MSB first 0x06 Unused 24 U Unused 0x07 Unused 24 U Unused 0x08 MOD 24 R/W Delta-Sigma Modulators Output Value 0x09 PHASE0 24 R/W Phase Delay Configuration Register - Channel pairs 4/5 0x0A PHASE1 24 R/W Phase Delay Configuration Register - Channel pairs 0/1 and 2/3 0x0B GAIN 24 R/W Gain Configuration Register 0x0C STATUSCOM 24 R/W Status and Communication Register 0x0D CONFIG0 24 R/W Configuration Register 0x0E CONFIG1 24 R/W Configuration Register 0x0F OFFCAL_CH0 24 R/W Offset Correction Register - Channel 0 0x10 GAINCAL_CH0 24 R/W Gain Correction Register - Channel 0 0x11 OFFCAL_CH1 24 R/W Offset Correction Register - Channel 1 0x12 GAINCAL_CH1 24 R/W Gain Correction Register - Channel 1 0x13 OFFCAL_CH2 24 R/W Offset Correction Register - Channel 2 0x14 GAINCAL_CH2 24 R/W Gain Correction Register - Channel 2 0x15 OFFCAL_CH3 24 R/W Offset Correction Register - Channel 3 0x16 GAINCAL_CH3 24 R/W Gain Correction Register - Channel 3 0x17 OFFCAL_CH4 24 R/W Offset Correction Register - Channel 4 0x18 GAINCAL_CH4 24 R/W Gain Correction Register - Channel 4 0x19 OFFCAL_CH5 24 R/W Offset Correction Register - Channel 5 0x1A GAINCAL_CH5 24 R/W Gain Correction Register - Channel 5 0x1B Unused 24 U Unused 0x1C Unused 24 U Unused 0x1D Unused 24 U Unused 0x1E Unused 24 U Unused 0x1F LOCK/CRC 24 R/W Security Register (Password and CRC-16 on Register Map) |
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