VPC3230D datasheet(29/78 Pages) MICRONAS

29 / 78 page

ADVANCE INFORMATION

VPC 323xD, VPC 324xD

Micronas

2.12.9. External Field Memory

The requirements of the external field memory are:

– FIFO type access with reset

– write mask function: The increasing of the write

address pointer and the over writing of the data

should be controlled separately.

– output disable function: tri-statetable outputs

For PIP applications, VPC 32xxD supports 4:1:1 or

4:2:2 chrominance format. Table 2–13 shows the typi-

cal memory size for a 13.5 and 16 MHz system clock

application.

The following 5 signals are generated by VPC 32xxD

to control the external field memory:

RSTWR (reset write/read) resets the internal write/

read address pointer to zero.

WE (write enable) is used to enable or disable incre-

menting of the internal write address pointer.

IE (input enable) is used to enable writing data from

the field memory input pins into the memory core, or to

disable writing and thereby preserving the previous

content of the memory (write mask function).

RE (read enable) is used to enable or disable incre-

menting the internal read address pointer.

OE (output enable) is used to enable or disable data

output to the output pins.

As serial write and serial read clock (SWCK and

SRCK, respectively) of the field memory the line

locked clocks LLC1 and/or LLC2 are used.

Table 2–12: Settings for Free-Running Mode

Control bit

Function

VPCsingle

VPCpip

VPCmain

write

PIP

write main

pic.

predef.

mode 6, 10

all other

modes

bit[11] of LLC_CLKC

(FP h’6a)

enable/disable

LLC PLL

100

bit[15] of AVO START

(I2C h’28)

enable/disable free-

running sync mode

100

Table 2–13: Word length and minimum size of the field

memory

Chromi-

nance

format

Word

length

Memory size

[bit]

[word]

[bit]

4:1:1

245376

2944512

4:2:2

245376

3926016

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