| поискавой системы для электроныых деталей |
|
VPC3230D датащи(PDF) 47 Page - Micronas |
|
|
|||||||||||||||||||||||||||||
VPC3230D датащи(HTML) 47 Page - Micronas |
|
47 / 78 page ![]() ADVANCE INFORMATION VPC 323xD, VPC 324xD Micronas 47 Table 3–3: Control Registers of the Fast Processor that are used for the control of DDP 3300A – this function is only available in the 50 Hz version (VPC 324xD) – default values are initialized at reset – * indicates: register is initialized according to the current standard when SDT register is changed FP Sub- address Function Default Name FP Display Control Register h’130 White Drive Red (0...1023) 700 WDR 1) h’131 White Drive Green (0...1023) 700 WDG 1) h’132 White Drive Blue (0...1023) 700 WDB 1) h’139 Internal Brightness, Picture (0 ..511), the center value is 256, the range allows for both increase and reduction of brightness. 256 IBR h’13c Internal Brightness, measurement (0...511), the center value is 256, the brightness for measurement can be set to measure at higher cutoff current. The measurement brightness is independent of the drive val- ues. 256 IBRM h’13a Analog Brightness for external RGB (0...511), the center value is 256, the range allows for both increase and reduction of brightness. 256 ABR h’13b Analog Contrast for external RGB (0...511) 350 ACT 1) The white drive values will become active only after writing the blue value WDB, latching of new values is indi- cated by setting the MSB of WDB. FP Display Control Register, BCL h’144 BCL threshold current, 0...2047 (max ADC output ~1152) 1000 BCLTHR h’142 BCL time constant 0...15 →13 ... 1700 msec 15 BCLTM h’143 BCL loop gain. 0..15 0 BCLG h’145 BCL minimum contrast 0 ...1023 307 BCLMIN h’105 Test register for BCL/EHT comp. function, register value: 0 normal operation 1 stop ADC offset compensation x>1 use x in place of input from Measurement ADC 0BCLTST FP Display Control Register, Deflection h’103 interlace offset, –2048 ...2047 This value is added to the SAWTOOTH output during one field. 0INTLC h’102 discharge sample count for deflection retrace, SAWTOOTH DAC output impedance is reduced for DSCC lines after vertical retrace. 7DSCC h’11f vertical discharge value, SAWTOOTH output value during discharge operation, typically same as A0 init value for sawtooth. –1365 DSCV h’10b EHT (electronic high tension) compensation coefficient, 0...511 0 EHT h’10a EHT time constant. 0 ..15 → 3.2 ...410 msec 15 EHTTM |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |