VPC3230D datasheet(22/78 Pages) MICRONAS

22 / 78 page

VPC 323xD, VPC 324xD

ADVANCE INFORMATION

Micronas

2.11. Video Sync Processing

Fig. 2–18 shows a block diagram of the front-end sync

processing. To extract the sync information from the

video signal, a linear phase lowpass filter eliminates all

noise and video contents above 1 MHz. The sync is

separated by a slicer; the sync phase is measured. A

variable window can be selected to improve the noise

immunity of the slicer. The phase comparator mea-

sures the falling edge of sync, as well as the integrated

sync pulse.

The sync phase error is filtered by a phase-locked loop

that is computed by the FP. All timing in the front-end is

derived from a counter that is part of this PLL, and it

thus counts synchronously to the video signal.

A separate hardware block measures the signal back

porch and also allows gathering the maximum/mini-

mum of the video signal. This information is processed

by the FP and used for gain control and clamping.

For vertical sync separation, the sliced video signal is

integrated. The FP uses the integrator value to derive

vertical sync and field information.

The information extracted by the video sync process-

ing is multiplexed onto the hardware front sync signal

(FSY) and is distributed to the rest of the video pro-

cessing system. The format of the front sync signal is

given in Fig. 2–19.

The data for the vertical deflection, the sawtooth, and

the East-West correction signal is calculated by the

VPC 32xx. The data is buffered in a FIFO and trans-

ferred to the back-end IC DDP 3300A by a single wire

interface.

Frequency and phase characteristics of the analog

video signal are derived from PLL1. The results are fed

to the scaler unit for data interpolation and orthogonal-

ization and to the clock synthesizer for line-locked

clock generation. Horizontal and vertical syncs are

latched with the line-locked clock.

Fig. 2–18: Sync separation block diagram

Fig. 2–19: Front sync format

phase

comparator

lowpass

counter

frontend

timing

front sync

lowpass

1 MHz

syncslicer

horizontal

sync

separation

vertical

sync

separation

FIFO

Sawtooth

video

input

skew

front

sync

generator

vertical

serial

data

vertical

sawtooth

E/W

Parabola

Calculation

clamping, colorkey, FIFO_write

PLL1

clamp &

signal

meas.

vblank

field

clock

synthesizer

syncs

clock

H/V syncs

input

analog

video

FSY

skew

LSB

not

used

MSB

(not in scale)

F0 reserved

0 = field 1

1 = field 2

F: field #

0 = off

1 = on

V: vertical sync

Parity

VPC3230D датащи(PDF) 22 Page - Micronas

VPC3230D датащи(HTML) 22 Page - Micronas

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

датащи скачать

ссылки URL