VPC3230D datasheet(40/78 Pages) MICRONAS

40 / 78 page

VPC 323xD, VPC 324xD

ADVANCE INFORMATION

Micronas

Table 3–2: Control Registers of the Fast Processor

– default values are initialized at reset

– * indicates: register is initialized according to the current standard when SDT register is changed.

FP Sub-

address

Function

Default

Name

Standard Selection

h’20

Standard select:

bit[2:0]

standard

PAL B,G,H,I

(50 Hz)

4.433618

NTSC M

(60 Hz)

3.579545

SECAM

(50 Hz)

4.286

NTSC44

(60 Hz)

4.433618

PAL M

(60 Hz)

3.575611

PAL N

(50 Hz)

3.582056

PAL 60

(60 Hz)

4.433618

NTSC COMB

(60 Hz)

3.579545

bit[3]

0/1

MOD standard modifier

PAL modified to simple PAL

NTSC modified to compensated NTSC

SECAM modified to monochrome 625

NTSCC modified to monochrome 525

bit[4]

0/1

PAL+ mode off/on

bit[5]

0/1

4-H COMB mode

bit[6]

0/1

S-VHS mode:

The S-VHS/COMB bits allow the following modes:

composite input signal

comb filter active

S-VHS input signal

CVBS mode (composite input signal, no luma notch)

Option bits allow to suppress parts of the initialization; this can be

used for color standard search:

bit[7]

no hpll setup

bit[8]

no vertical setup

bit[9]

no acc setup

bit[10]

4-H comb filter setup only

bit[11]

status bit, normally write 0. After the FP has switched to a

new standard, this bit is set to 1 to indicate operation

complete. Standard is automatically initialized when the

insel register is written.

SDT

PAL

NTSC

SECAM

NTSC44

PALM

PALN

PAL60

NTSCC

SDTMOD

PALPLUS

COMB

SVHS

SDTOPT

h’148

Enable automatic standard recognition

bit[0]

0/1

PAL B,G,H,I

(50 Hz)

4.433618

bit[1]

0/1

NTSC M

(60 Hz)

3.579545

bit[2]

0/1

SECAM

(50 Hz)

4.286

bit[3]

0/1

NTSC44

(60 Hz)

4.433618

bit[4]

0/1

PAL M

(60 Hz)

3.575611

bit[5]

0/1

PAL N

(50 Hz)

3.582056

bit[6]

0/1

PAL 60

(60 Hz)

4.433618

0: disable recognition; 1: enable recognition

0ASR_ENABLE

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