ADV7181BBCPZ datasheet(24/96 Pages) AD

24 / 96 page

ADV7181B

Rev. 0 | Page 24 of 96

DEF_VAL_EN Default Value Enable, Address 0x0C [0]

This bit forces the use of the default values for Y, Cr, and Cb.

Refer to the descriptions for DEF_Y and DEF_C for additional

information. In this mode, the decoder also outputs a stable

27 MHz clock, HS, and VS.

Setting DEF_VAL_EN to 0 (default) outputs a colored screen

determined by user programmable Y, Cr, and Cb values when

the decoder free-runs. Free-run mode is turned on and off by

the DEF_VAL_AUTO_EN bit.

Setting DEF_VAL_EN to 1 forces a colored screen output

determined by user programmable Y, Cr, and Cb values. This

overrides picture data even if the decoder is locked.

DEF_VAL_AUTO_EN Default Value Automatic Enable,

Address 0x0C [1]

This bit enables the automatic use of the default values for Y, Cr,

and Cb when the ADV7181B cannot lock to the video signal.

Setting DEF_VAL_AUTO_EN to 0 disables free-run mode. If

the decoder is unlocked, it outputs noise.

Setting DEF_VAL_EN to 1 (default) enables free-run mode, and

a colored screen set by user programmable Y, Cr and Cb values

is displayed when the decoder loses lock.

CLAMP OPERATION

The input video is ac-coupled into the ADV7181B. Therefore,

its dc value needs to be restored. This process is referred to as

clamping the video. This section explains the general process of

clamping on the ADV7181B, and shows the different ways in

which a user can configure its behavior.

The ADV7181B uses a combination of current sources and a

digital processing block for clamping, as shown in Figure 9. The

analog processing channel shown is replicated three times

inside the IC. While only one single channel (and only one

ADC) would be needed for a CVBS signal, two independent

channels are needed for YC (S-VHS) type signals, and three

independent channels are needed to allow component signals

(YPrPb) to be processed.

The clamping can be divided into two sections:

•

Clamping before the ADC (analog domain): current

sources.

•

Clamping after the ADC (digital domain): digital

processing block.

The ADCs can digitize an input signal only if it resides within

the ADC’s 1.6 V input voltage range. An input signal with a dc

level that is too large or too small is clipped at the top or bottom

of the ADC range.

The primary task of the analog clamping circuits is to ensure

that the video signal stays within the valid ADC input window

so that the analog-to-digital conversion can take place. It is not

necessary to clamp the input signal with a very high accuracy in

the analog domain as long as the video signal fits the ADC range.

After digitization, the digital fine clamp block corrects for any

remaining variations in dc level. Since the dc level of an input

video signal refers directly to the brightness of the picture

transmitted, it is important to perform a fine clamp with high

accuracy; otherwise, brightness variations may occur. Further-

more, dynamic changes in the dc level almost certainly lead to

visually objectionable artifacts, and must therefore be prohibited.

The clamping scheme has to complete two tasks. It must be able

to acquire a newly connected video signal with a completely

unknown dc level, and it must maintain the dc level during

normal operation.

For quickly acquiring an unknown video signal, the large current

clamps may be activated. Note that it is assumed that the ampli-

tude of the video signal at this point is of a nominal value.

Control of the coarse and fine current clamp parameters is

performed automatically by the decoder.

Standard definition video signals may have excessive noise on

them. In particular, CVBS signals transmitted by terrestrial

broadcast and demodulated using a tuner usually show very

large levels of noise (>100 mV). A voltage clamp would be

unsuitable for this type of video signal. Instead, the ADV7181B

employs a set of four current sources that can cause coarse

(>0.5 mA) and fine (<0.1 mA) currents to flow into and away

from the high impedance node that carries the video signal (see

Figure 9).

COARSE

CURRENT

SOURCES

FINE

CURRENT

SOURCES

DATA

PRE-

PROCESSOR

(DPP)

ADC

SDP

WITH DIGITAL

FINE CLAMP

CLAMP CONTROL

ANALOG

VIDEO

INPUT

Figure 9. Clamping Overview

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