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ADV7181BBCPZ датащи(PDF) 78 Page - Analog Devices |
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ADV7181BBCPZ датащи(HTML) 78 Page - Analog Devices |
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78 / 96 page ![]() ADV7181B Rev. 0 | Page 78 of 96 Bits Subaddress Register Bit Description 7 6 5 4 3 210 Comments Notes CMG[11:8]. Chroma manual gain can be used to program a desired manual chroma gain. Reading back from this register in AGC mode gives the current gain. 0 1 0 0 CAGC[1:0] settings decide in which mode CMG[11:0] operates Reserved 1 1 Set to 1 00 Slow (TC = 2 s) 01 Medium (TC = 1 s) 1 0 Fast (TC = 0.2 s) 0x2D Chroma Gain Control 1 CAGT[1:0]. Chroma automatic gain timing allows adjustment of the chroma AGC tracking speed. 1 1 Adaptive Has an effect only if CAGC[1:0] is set to auto gain (10) 0x2E Chroma Gain Control 2 CMG[7:0]. Chroma manual gain lower 8 bits. See CMG[11:8] for description. 0 0 0 0 0 0 0 0 CMG[11:0] = 750d; gain is 1 in NTSC CMG[11:0] = 741d; gain is 1 in PAL Min value is 0dec (G = –60 dB) Max value is 3750 (Gain = 5) LMG[11:8]. Luma manual gain can be used program a desired manual chroma gain, or to read back the actual gain value used. x x x x LAGC[1:0] settings decide in which mode LMG[11:0] operates Reserved 1 1 Set to 1 00 Slow (TC = 2 s) 01 Medium (TC = 1 s) 1 0 Fast (TC = 0.2 s) 0x2F Luma Gain Control 1 LAGT[1:0]. Luma automatic gain timing allows adjustment of the luma AGC tracking speed. 1 1 Adaptive Only has an effect if LAGC[1:0] is set to auto gain (001, 010, 011,or 100) 0x30 Luma Gain Control 2 LMG[7:0]. Luma manual gain can be used to program a desired manual chroma gain or read back the actual used gain value. x x x x x x x x LMG[11:0] = 1234d; gain is 1 in NTSC LMG[11:0] = 1266d; gain is 1 in PAL Min value NTSC 1024 (G = 0.85) PAL (G = 0.81) Max value NTSC 2468 (G = 2), PAL = 2532 (G = 2) 0x31 Reserved 0 1 0 Set to default 0 Start of line relative to HSE HSE = Hsync end HVSTIM. Selects where within a line of video the VS signal is asserted. 1 Start of line relative to HSB HSB = Hsync begin 0 EAV/SAV codes generated to suit ADI encoders NEWAVMODE. Sets the EAV/SAV mode. 1 Manual VS/Field position controlled by registers 0x32, 0x33, and 0xE5–0xEA VS and FIELD Control 1 Reserved 0 0 0 Set to default Reserved 0 0 0 0 0 1 Set to default VSBHE 0 VS goes high in the middle of the line (even field) 1 VS changes state at the start of the line (even field) VSBHO 0 VS goes high in the middle of the line (odd field) 0x32 VSync Field Control 2 1 VS changes state at the start of the line (odd field) NEWAVMODE bit must be set high. Reserved 0 0 0 1 0 0 Set to default VSEHE 0 VS goes low in the middle of the line (even field) 1 VS changes state at the start of the line (even field) 0 VS goes low in the middle of the line (odd field) 0x33 VSync Field Control 3 VSEHO 1 VS changes state at the start of the line odd field NEWAVMODE bit must be set high. |
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