ADV7181BBCPZ datasheet(22/96 Pages) AD

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ADV7181B

Rev. 0 | Page 22 of 96

SRLS Select Raw Lock Signal, Address 0x51 [6]

Using the SRLS bit, the user can choose between two sources for

determining the lock status (per Bits [1:0] in the Status 1 register).

•

The time_win signal is based on a line-to-line evaluation of

the horizontal synchronization pulse of the incoming

video. It reacts quite quickly.

•

The free_run signal evaluates the properties of the

incoming video over several fields, and takes vertical

synchronization information into account.

Setting SRLS to 0 (default) selects the free_run signal.

Setting SRLS to 1 selects the time_win signal.

FSCLE Fsc Lock Enable, Address 0x51 [7]

The FSCLE bit allows the user to choose whether the status of

the color subcarrier loop is taken into account when the overall

lock status is determined and presented via Bits [1:0] in Status

ADV7181B in YPrPb component mode in order to generate a

reliable HLOCK status bit.

When FSCLE is set to 0 (default), the overall lock status only is

dependent on horizontal sync lock.

When FSCLE is set to 1, the overall lock status is dependent on

horizontal sync lock and Fsc Lock.

CIL[2:0] Count Into Lock, Address 0x51 [2:0]

CIL[2:0] determines the number of consecutive lines for which

the into lock condition must be true before the system switches

into the locked state, and reports this via Status 0 [1:0]. It counts

the value in lines of video.

Table 18. CIL Function

CIL[2:0]

Description

000

001

010

011

100 (default)

100

101

500

110

1000

111

100000

COL[2:0] Count Out of Lock, Address 0x51 [5:3]

COL[2:0] determines the number of consecutive lines for which

the out of lock condition must be true before the system

switches into unlocked state, and reports this via Status 0 [1:0].

It counts the value in lines of video.

Table 19. COL Function

COL[2:0]

Description

000

001

010

011

100 (default)

100

101

500

110

1000

111

100000

COLOR CONTROLS

These registers allow the user to control picture appearance,

including control of the active data in the event of video being

lost. These controls are independent of any other controls. For

instance, brightness control is independent from picture

clamping, although both controls affect the signal’s dc level.

CON[7:0] Contrast Adjust, Address 0x08 [7:0]

This register allows the user to control contrast adjustment of

the picture.

Table 20. CON Function

CON[7:0]

Description

0x80 (default)

Gain on luma channel = 1.

0x00

Gain on luma channel = 0.

0xFF

Gain on luma channel = 2.

SD_SAT_Cb[7:0] SD Saturation Cb Channel,

Address 0xE3 [7:0]

This register allows the user to control the gain of the Cb

channel only, which in turn adjusts the saturation of the picture.

Table 21. SD_SAT_Cb Function

SD_SAT_Cb[7:0]

Description

0x80 (default)

Gain on Cb channel = 0 dB.

0x00

Gain on Cb channel = −42 dB.

0xFF

Gain on Cb channel = +6 dB.

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