ADV7181BBCPZ datasheet(69/96 Pages) AD

69 / 96 page

ADV7181B

Rev. 0 | Page 69 of 96

Bit

Subaddress

Bit Description

Comments

Notes

SD 60 Hz signal output

SD_OP_50Hz

SD 60/50Hz frame rate at

output

SD 50 Hz signal output

SD vertical sync lock not

established

SD_V_LOCK

SD vertical sync lock

established

SD horizontal sync lock not

established

SD_H_LOCK

SD horizontal sync lock

established

Reserved

Not used

SECAM Lock not established

SCM_LOCK

SECAM Lock

SECAM Lock established

Reserved

Not used

Reserved

Not used

0x49

Raw

Status 3

Read Only

Access

Page 2

Reserved

Not used

These bits

cannot be

cleared or

masked.

0x4A is used

for this

purpose.

No Change in SD signal

standard detected at the input

SD_OP_CHNG_Q

SD 60/50 Hz frame rate at

input

A Change in SD signal standard

is detected at the input

No Change in SD vertical sync

lock status

SD_V_LOCK_CHNG_Q

SD vertical sync lock status has

changed.

No change in SD horizontal sync

lock status.

SD_H_LOCK_CHNG_Q

SD horizontal sync lock status

has changed

No change in AD_RESULT[2:0]

bits in Status Register 1.

SD_AD_CHNG_Q

SD autodetect changed

AD_RESULT[2:0] bits in Status

No Change in SECAM Lock

status

SCM_LOCK_CHNG_Q

SECAM Lock

SECAM lock status has changed

No change in PAL swinging

burst lock status

PAL_SW_LK_CHNG_Q

PAL swinging burst lock status

has changed

Reserved

Not used

0x4A

Interrupt

Status 3

Read Only

Access

Page 2

Reserved

Not used

These bits

can be

cleared and

masked by

registers

0x4B and

0x4C,

respectively.

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