ADV7181BBCPZ datasheet(46/96 Pages) AD

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ADV7181B

Rev. 0 | Page 46 of 96

VBI DATA DECODE

The following low data rate VBI signals can be decoded by the

ADV7181B:

•

Wide screen signaling (WSS)

•

Copy generation management systems (CGMS)

•

Closed captioning (CCAP)

•

EDTV

•

Gemstar 1×- and 2×-compatible data recovery

The presence of any of the above signals is detected and, if

applicable, a parity check is performed. The result of this testing

is contained in a confidence bit in the VBI Info[7:0] register.

Users are encouraged to first examine the VBI Info register

before reading the corresponding data registers. All VBI data

decode bits are read-only.

All VBI data registers are double-buffered with the field signals.

This means that data is extracted from the video lines and

appears in the appropriate I2C registers with the next field

transition. They are then static until the next field.

The user should start an I2C read sequence with VS by first

examining the VBI Info register. Then, depending on what data

was detected, the appropriate data registers should be read.

The data registers are filled with decoded VBI data even if their

corresponding detection bits are low; it is likely that bits within

the decoded data stream are wrong.

The closed captioning data (CCAP) is available in the I2C

registers, and is also inserted into the output video data stream

during horizontal blanking.

The Gemstar-compatible data is not available in the I2C

registers, and is inserted into the data stream only during

horizontal blanking.

WSSD Wide Screen Signaling Detected, Address 0x90 [0]

Logic 1 for this bit indicates that the data in the WSS1 and

WSS2 registers is valid.

The WSSD bit goes high if the rising edge of the start bit is

detected within a time window, and if the polarity of the parity

bit matches the transmitted data.

When WSSD is 0, no WSS is detected and confidence in the

decoded data is low.

When WSSD is 1, WSS is detected and confidence in the

decoded data is high.

CCAPD Closed Caption Detected, Address 0x90 [1]

Logic 1 for this bit indicates that the data in the CCAP1 and

CCAP2 registers is valid.

The CCAPD bit goes high if the rising edge of the start bit is

detected within a time window, and if the polarity of the parity

bit matches the transmitted data.

When CCAPD is 0, no CCAP signals are detected and

confidence in the decoded data is low.

When CCAPD is 1, the CCAP sequence is detected and

confidence in the decoded data is high.

EDTVD EDTV Sequence Detected, Address 0x90 [2]

Logic 1 for this bit indicates that the data in the EDTV1, 2, 3

registers is valid.

The EDTVD bit goes high if the rising edge of the start bit is

detected within a time window, and if the polarity of the parity

bit matches the transmitted data.

When EDTVD is 0, no EDTV sequence is detected. Confidence

in decoded data is low.

When EDTVD is 1, an EDTV sequence is detected. Confidence

in decoded data is high.

CGMSD CGMS-A Sequence Detected, Address 0x90 [3]

Logic 1 for this bit indicates that the data in the CGMS1, 2, 3

registers is valid. The CGMSD bit goes high if a valid CRC

checksum has been calculated from a received CGMS packet.

When CGMSD is 0, no CGMS transmission is detected and

confidence in decoded data is low.

When CGMSD is 1, the CGMS sequence is decoded and

confidence in decoded data is high.

CRC_ENABLE CRC CGMS-A Sequence, Address 0xB2 [2]

For certain video sources, the CRC data bits may have an

invalid format. In such circumstances, the CRC checksum

validation procedure can be disabled. The CGMSD bit goes

high if the rising edge of the start bit is detected within a time

window.

When CRC_ENABLE is 0, no CRC check is performed. The

CGMSD bit goes high if the rising edge of the start bit is

detected within a time window.

When CRC_ENABLE is 1 (default), CRC checksum is used to

validate the CGMS sequence. The CGMSD bit goes high for a

valid checksum. ADI recommended setting.

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