HT46C64 datasheet(14/47 Pages) HOLTEK

14 / 47 page

HT46R64/HT46C64

Rev. 1.40

September 21, 2004

Time Base

The time base offers a periodic time-out period to gener-

ate a regular internal interrupt. Its time-out period

ranges from 2

12/f

S to 2

15/f

S selected by options. If time

base time-out occurs, the related interrupt request flag

(TBF; bit 5 of INTC1) is set. But if the interrupt is en-

abled, and the stack is not full, a subroutine call to loca-

tion 14H occurs.

Real Time Clock

- RTC

The real time clock (RTC) is operated in the same man-

ner as the time base that is used to supply a regular in-

ternal interrupt. Its time-out period ranges from fS/2

8 to

fS/2

15 by software programming . Writing data to RT2,

RT1 and RT0 (bit 2, 1, 0 of RTCC;09H) yields various

time-out periods. If the RTC time-out occurs, the related

interrupt request flag (RTF; bit 6 of INTC1) is set. But if

the interrupt is enabled, and the stack is not full, a sub-

routine call to location 18H occurs.

RT2

RT1

RT0

RTC Clock Divided Factor

000

001

010

10*

011

11*

100

101

110

111

Note:

²*² not recommended to be used

Power Down Operation

- HALT

The HALT mode is initialized by the

²HALT² instruction

and results in the following.

· The system oscillator turns off but the WDT oscillator

keeps running (if the WDT oscillator or the real time

clock is selected).

· The contents of the on-chip RAM and of the registers

remain unchanged.

· The WDT is cleared and start recounting (if the WDT

clock source is from the WDT oscillator or the real time

clock oscillator).

· All I/O ports maintain their original status.

· The PDF flag is set but the TO flag is cleared.

· LCD driver is still running (if the WDT OSC or RTC

OSC is selected).

The system quits the HALT mode by an external reset,

an interrupt, an external falling edge signal on port A, or

a WDT overflow. An external reset causes device initial-

ization, and the WDT overflow performs a

²warm reset².

After examining the TO and PDF flags, the reason for

chip reset can be determined. The PDF flag is cleared by

system power-up or by executing the

²CLR WDT² in-

struction, and is set by executing the

²HALT² instruction.

On the other hand, the TO flag is set if WDT time-out oc-

curs, and causes a wake-up that only resets the PC (Pro-

gram Counter) and SP, and leaves the others at their

original state.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake up the

device by options. Awakening from an I/O port stimulus,

the program resumes execution of the next instruction.

On the other hand, awakening from an interrupt, two se-

quence may occur. If the related interrupt is disabled or

the interrupt is enabled but the stack is full, the program

resumes execution at the next instruction. But if the in-

terrupt is enabled, and the stack is not full, the regular in-

terrupt response takes place.

D i v i d e r

f S

8 t o 1

M u x .

P r e s c a l e r

R T 2

R T 1

R T 0

R T C I n t e r r u p t

2 8 / f S ~ 2 1 5 / f S

Real Time Clock

f s

D i v i d e r

P r e s c a l e r

O p t i o n

L C D D r i v e r ( f S / 2 2 ~ f S / 2 8 )

B u z z e r ( f S / 2 2 ~ f S / 2 9 )

T i m e B a s e I n t e r r u p t

2 1 2 / f S ~ 2 1 5 / f S

O p t i o n

Time Base

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