HT46C64 datasheet(9/47 Pages) HOLTEK

9 / 47 page

HT46R64/HT46C64

Rev. 1.40

September 21, 2004

These areas may function as a normal ROM depend-

ing upon the user

¢s requirements.

Stack Register

- STACK

The stack register is a special part of the memory used

to save the contents of the PC. The stack is organized

into 8 levels and is neither part of the data nor part of the

program, and is neither readable nor writeable. Its acti-

vated level is indexed by a stack pointer (SP) and is nei-

ther readable nor writeable. At the start of a subroutine

call or an interrupt acknowledgment, the contents of the

PC is pushed onto the stack. At the end of the subrou-

tine or interrupt routine, signaled by a return instruction

(RET or RETI), the contents of the PC is restored to its

previous value from the stack. After chip reset, the SP

will point to the top of the stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag is recorded but the ac-

knowledgment is still inhibited. Once the SP is decre-

mented (by RET or RETI), the interrupt is serviced. This

feature prevents stack overflow, allowing the program-

mer to use the structure easily. Likewise, if the stack is

full, and a

²CALL² is subsequently executed, a stack

overflow occurs and the first entry is lost (only the most

recent sixteen return addresses are stored).

Data Memory

- RAM

The data memory (RAM) is designed with 224

´8 bits,

and is divided into two functional groups, namely; spe-

cial function registers 32

´8 bit and general purpose data

memory, 192

´8 bit most of which are readable/writable,

although some are read only. The special function regis-

ter are overlapped in any banks.

Of the two types of functional groups, the special func-

tion registers consist of an Indirect addressing register 0

(00H), a Memory pointer register 0 (MP0;01H), an Indi-

rect addressing register 1 (02H), a Memory pointer reg-

ister 1 (MP1;03H), a Bank pointer (BP;04H), an

Accumulator (ACC;05H), a Program counter

lower-order byte register (PCL;06H), a Table pointer

(TBLP;07H), a Table higher-order byte register

(TBLH;08H), a Real time clock control register

(RTCC;09H), a Status register (STATUS;0AH), an Inter-

rupt control register 0 (INTC0;0BH), a Timer/Event

Counter 0 (TMR0; 0DH), a Timer/Event Counter 0 con-

trol register (TMR0C;0EH), a Timer/Event Counter 1

(TMR1H:0FH;TMR1L:10H), a Timer/Event Counter 1

control register (TMR1C; 11H), Interrupt control register

1 (INTC1;1EH), PWM data register (PWM0;1AH,

PWM1;1BH, PWM2;1CH, PWM3;1DH), the A/D result

lower-order byte register (ADRL;24H), the A/D result

higher-order byte register (ADRH;25H), the A/D control

(ACSR;27H), I/O registers (PA;12H, PB;14H, PD;18H)

and I/O control registers (PAC;13H, PBC;15H,

PDC;19H). The remaining space before the 40H is re-

served for future expanded usage and reading these lo-

cations will get

²00H². The space before 40H is

overlapping in each bank. The general purpose data

memory, addressed from 40H to FFH, is used for data

and control information under instruction commands. All

of the data memory areas can handle arithmetic, logic,

increment, decrement and rotate operations directly.

Except for some dedicated bits, each bit in the data

memory can be set and reset by

²SET [m].i² and ²CLR

S p e c i a l P u r p o s e

D a t a M e m o r y

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

G e n e r a l P u r p o s e

D a t a M e m o r y

( 1 9 2 B y t e s )

F F H

4 0 H

2 0 H

2 1 H

2 2 H

2 3 H

2 4 H

2 5 H

2 6 H

2 7 H

2 8 H

3 F H

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

M P 0

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

M P 1

B P

A C C

P C L

T B L P

T B L H

R T C C

S T A T U S

I N T C 0

T M R 0

T M R 0 C

T M R 1 H

T M R 1 L

T M R 1 C

P A

P A C

P B

P B C

P D

P D C

P W M 0

P W M 1

P W M 2

P W M 3

I N T C 1

A D R L

A D R H

A D C R

A C S R

: U n u s e d

R e a d a s " 0 0 "

RAM Mapping

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