HT46C64 datasheet(12/47 Pages) HOLTEK

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HT46R64/HT46C64

Rev. 1.40

September 21, 2004

set, a subroutine call to location 14H occurs. The related

interrupt request flag (TBF) is reset and the EMI bit is

cleared to disable further maskable interrupts.

The real time clock interrupt is initialized by setting the

real time clock interrupt request flag (RTF; bit 6 of

INTC1), that is caused by a regular real time clock sig-

nal. After the interrupt is enabled, and the stack is not

full, and the RTF bit is set, a subroutine call to location

18H occurs. The related interrupt request flag (RTF) is

reset and the EMI bit is cleared to disable further

maskable interrupts.

During the execution of an interrupt subroutine, other

maskable interrupt acknowledgments are all held until

the

²RETI² instruction is executed or the EMI bit and the

related interrupt control bit are set both to 1 (if the stack

is not full). To return from the interrupt subroutine,

²RET²

²RETI² may be invoked. RETI sets the EMI bit and en-

ables an interrupt service, but RET does not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses are serviced on the

latter of the two T2 pulses if the corresponding interrupts

are enabled. In the case of simultaneous requests, the

priorities in the following table apply. Except for A/D con-

verter interrupt (NMI). These can be masked by reset-

ting the EMI bit.

Interrupt Source

Priority

Vector

External interrupt 0

04H

External interrupt 1

08H

Timer/Event Counter 0 overflow

0CH

Timer/Event Counter 1 overflow

10H

Time base interrupt

14H

Real time clock interrupt

18H

A/D converter interrupt (This is a

Non-Maskable Interrupt: NMI)

1CH

The Timer/Event Counter 0 interrupt request flag (T0F),

external interrupt 1 request flag (EIF1), external inter-

rupt 0 request flag (EIF0), enable Timer/Event Counter

0 interrupt bit (ET0I), enable external interrupt 1 bit

(EEI1), enable external interrupt 0 bit (EEI0), enable

master interrupt bit (EMI), and enable control the A/D

converter interrupt (EADI) make up of the Interrupt Con-

trol register 0 (INTC0) which is located at 0BH in the

RAM. The real time clock interrupt request flag (RTF),

time base interrupt request flag (TBF), Timer/Event

Counter 1 interrupt request flag (T1F), enable real time

clock interrupt bit (ERTI), and enable time base interrupt

bit (ETBI), enable Timer/Event Counter 1 interrupt bit

(ET1I) on the other hand, constitute the Interrupt Control

EMI, EEI0, EEI1, ET0I, ET1I, ETBI, and ERTI are all

used to control the enable/disable status of interrupts.

These bits prevent the requested interrupt from being

serviced. Once the interrupt request flags (RTF, TBF,

T0F, T1F, EIF1, EIF0) are all set, they remain in the

INTC1 or INTC0 respectively until the interrupts are ser-

viced or cleared by a software instruction.

It is recommended that a program should not use the

²CALL subroutine² within the interrupt subroutine. It¢sbe-

cause interrupts often occur in an unpredictable manner

or require to be serviced immediately in some applica-

tions. During that period, if only one stack is left, and en-

abling the interrupt is not well controlled, operation of the

²call² in the interrupt subroutine may damage the origi-

nal control sequence.

Oscillator Configuration

The device provides three oscillator circuits for system

clocks, i.e., RC oscillator, crystal oscillator and 32768Hz

crystal oscillator, determined by options. No matter what

type of oscillator is selected, the signal is used for the

system clock. The HALT mode stops the system oscilla-

tor (RC and crystal oscillator only) and ignores external

signal in order to conserve power. The 32768Hz crystal

oscillator still runs at HALT mode. If the 32768Hz crystal

oscillator is selected as the system oscillator, the system

oscillator is not stopped; but the instruction execution is

stopped. Since the 32768Hz oscillator is also designed

for timing purposes, the internal timing (RTC, time base,

WDT) operation still runs even if the system enters the

HALT mode.

Of the three oscillators, if the RC oscillator is used, an

external resistor between OSC1 and VSS is required,

and the range of the resistance should be from 30k

W to

750k

W. The system clock, divided by 4, is available on

C r y s t a l O s c i l l a t o r

R C O s c i l l a t o r

O S C 1

O S C 2

f S Y S / 4

O S C 2

3 2 7 6 8 H z C r y s t a l / R T C O s c i l l a t o r

O S C 3

O S C 4

V D D

4 7 0 p F

System Oscillator

Note: *32768Hz crystal enable condition: For WDT clock source or for system clock source.

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