PC87591L datasheet(133/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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PS/2 Interrupt Enable Register (PSIEN)

The PSIEN register is an 8-bit read/write register. It enables/disables the various interrupts generated by the PS/2 module.

Bits in PSIEN register may be cleared to 0 only when interrupts are disabled (i.e., in the core, I or E bits in PSR register are

0) or when the corresponding interrupts in the ICU are masked. Bits in PSIEN register may be set to 1 at any time. On reset,

non-reserved bits of PSIEN are cleared.

Location: 00 FE8A16

Type: R/W

Bit

76543210

Name

Reserved

DSMIE

EOTIE

SOTIE

Reset

00000000

Bit

Description

SOTIE (Start of Transaction Interrupt Enable). Used for enabling the interrupt generation on a transaction

start detection.

0: SOT bit in PSTAT register does not affect the interrupt signal.

1: The interrupt signal (PSINT1) to the ICU is active (1) whenever SOT bit in PSTAT register is set.

Note: Once set, SOT is not cleared until the shift mechanism is reset. Therefore SOTIE should be cleared on

the ﬁrst occurrence of an SOT interrupt. SOTIE should be set (1) when the PS/2 module is programed to

handle the impending transfer.

EOTIE (End of Transaction Interrupt Enable). Used for enabling the interrupt generation on an End of

Transaction detection.

0: EOT bit in PSTAT register does not affect the interrupt signal.

1: The interrupt signal (PSINT1) to the ICU is active (1) whenever EOT bit in PSTAT register is set.

Note: Once set, EOT is not cleared until the shift mechanism is reset. Therefore EOTIE should be cleared on

the ﬁrst occurrence of an EOT interrupt. EOTIE should be set (1) when the PS/2 module is programed to

handle the impending transfer.

Disabled Shift Mechanism Interrupt Enable (DSMIE). Used for enabling the interrupt generation when the

shift mechanism is disabled.

0: The four interrupt signals are low. Note that PSINT1 may be activated (1) by other interrupt sources of the module.

1: The clock input signals are connected to the Interrupt Control Unit (ICU), to allow implementing an interrupt driv-

en PS/2 protocol. The four interrupts generated are PSINT1, PSINT2, PSINT3 and PSINT4, for channels 1, 2,

3 and 4, respectively. Note that PSINT4 is connected to the MIWU and not directly to the ICU.

Note: When the shift mechanism is disabled, no debounce is applied to the PSCLK inputs before producing the

interrupt signals, except for local synchronization.

7-3

Reserved.

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