PC87591L datasheet(129/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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PS/2 Register Map

PS/2 Data Register (PSDAT)

The PSDAT register is a byte-wide read/write register. In Receive mode, PSDAT holds the data received in the last message

from the PS/2 device. In Transmit mode, the data to be shifted out is written to this register. When the PS/2 i/f is reset, the

contents of this register become invalid.

On reset, the PS/2 interface is set to Receive mode. In this mode, PSDAT should be read only when EOT bit in PSTAT

Setting the transmit enable bit in PSCON register to 1 (XMT = 1 in PSCON register) puts the PS/2 interface in Transmit

mode. PSDAT should be written only when in Transmit mode and when all four channel enable bits CLK4-1 in PSOSIG reg-

ister are cleared (0).

Location: 00 FE8016

Type: R/W

PS/2 Status Register (PSTAT)

The PSTAT register is a byte-wide read-only register. It contains the status information on the data transfer on the PS/2

ports. All non-reserved bits of PSTAT are cleared (0) on reset when CLK1, CLK2 and CLK3 in PSOSIG are cleared and

when EN bit in PSCON register is cleared. Reading PSTAT does not clear any of its bits.

Location: 00 FE8216

Type: RO

Mnemonic

Type

PSDAT

PS/2 Data Register

R/W

PSTAT

PS/2 Status Register

PSCON

PS/2 Control Register

R/W

PSOSIG

PS/2 Output Signal Register

R/W

PSISIG

PS/2 Input Signal Register

PSIEN

PS/2 Interrupt Enable Register

R/W

Bit

76543210

Name

Data

Bit

Description

7-0

Data. Contains the data received in the last message (or that is transmitted in the following transmission). Bit 0

is the ﬁrst bit to be shifted (LSB).

Bit

76543210

Name

Reserved

RFERR

ACH

PERR

EOT

SOT

Reset

0000000

Bit

Description

SOT (Start of Transaction). When set to 1, indicates that a start bit was detected. The ACH ﬁeld (bits 5-3 of

this register) indicates which of the channels it was detected on.

EOT (End of Transaction). When set to 1, Indicates that a PS/2 data transfer was completed, i.e., a stop bit

was detected at Receive mode or a line control bit was detected at Transmit mode.

PERR (Parity Error).

When set to 1, indicates that a parity error was detected in the last data transfer.

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