PC87591L datasheet(135/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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4.7.2

Clock Source Unit

The clock source unit, as shown in Figure 45, contains two clock selectors for each counter and a 5-bit clock pre-scaler.

Pre-Scaler

The 5-bit clock pre-scaler consists of a pre-scaler register and a 5-bit counter, allowing the timer to run with a prescaled

clock. The system clock is divided by the value contained in TnPRSC+1. The minimum counter clock frequency is thus the

system clock divided by 32, and the maximum counter clock frequency is equal to the system clock. The pre-scaler register,

TnPRSC, can be read or written by software at any time. The pre-scaler counter is a 5-bit down counter which can not be

read or written by software. The 5-bit counter and the pre-scaler register TnPRSC are cleared on reset

External Event Clock

The TBn I/O pin can be selected as an external event input clock source for either of the two 16-bit counters. The polarity of

the input signal is programmable to trigger a count if either a rising or a falling edge is detected on TBn. The minimum pulse

width of the external signal is one system clock cycle; thus the maximum frequency with which the counter can run in this

mode is limited to half the system clock frequency.

Note: An External Event clock is not available in Dual Channel Capture mode because this mode requires TBn as an input.

Pulse Accumulate Mode

In Pulse Accumulate mode, the counter can also be clocked while an external signal on TBn is either high or low. In this

configuration, the output of the pre-scaler is gated with an external signal applied on TBn input. This mode can be used to

obtain a cumulative count of pre-scaler output clock pulses, as shown in Figure 46.

Note: Pulse Accumulate mode is not available in Dual Channel Capture mode because this mode requires TBn as an input.

Slow-Speed Clock

A slow-speed clock of 32.768 KHz can be used as a clock source for the two 16-bit counters. The MFT16 synchronizes the

slow-speed clock with the system clock. Therefore, the maximum input frequency of the slow-speed clock is the system clock

rate divided by four.

Some power save modes stop the system clock completely. When this occurs, the timer stops counting the slow-speed clock

until the system clock resumes. While operating in a power-save mode that uses a slow system clock, the slow-speed clock

source for the timer can only be used if it is at least four times faster than the slow- speed clock for the counter.

Pre-Scaler Register

TPRSC

Pre-Scaler Counter

5-Bit

System

Clock

Reset

TBn

Pulse

Accumulate

External

Event

No Clock

Prescaled

Clock

Counter 1

Clock

Select

Counter 2

Clock

Select

Counter 1

Clock

Counter 2

Clock

Synchr.

Slow Speed

Clock

Synchr.

Figure 45. Clock Pre-Scaler and Selector

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