PC87591L datasheet(137/437 Pages) NSC

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Embedded Controller Modules (Continued)

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Figure 47 shows a block diagram of the timer operating in mode 1. In PWM mode, counter 1, TnCNT1, functions as the time

base for the PWM timer. Counter 1 counts down at the clock rate selected via the counter 1 clock selector. When an under-

flow occurs, the timer register is reloaded alternately from the TnCRA and TnCRB registers, and counting proceeds down-

ward from the loaded value. On reset, and every time this mode is entered, the first reload in this mode is from the TnCRA

register. Once enabled, the counter starts counting down from the value currently loaded to it. At the first underflow, the timer

is loaded from TnCRA; on the second underflow, it is loaded from TnCRB; on the third underflow, it is loaded from TnCRA,

and so on. Note that every time the counter is stopped through the selection of “No-Clock” in the counter 1 clock selector

(TnCKC), it obtains its first reload value after it has been re-started from TnCRA register.

The timer can be configured to toggle TAn output bit on underflow. This results in the generation of a clock signal on TAn,

with the width and duty cycle controlled by the values stored in TnCRA and TnCRB registers. This PWM clock is processor-

independent because once the timer is set up, no more interaction is required by software (and therefore the CPU) to gen-

erate a continuous PWM signal. Software can select the initial value of the PWM output signal as either high or low. See

“Timer I/O Functions” on page 141 for additional details. The timer can be configured to generate separate interrupts on re-

load from TnCRA and TnCRB. The interrupts can be enabled or disabled under software control. The TAnPND or TnBPND

flags, respectively, which are set by the hardware on occurrence of a timer reload, indicate which interrupt occurred. See

Section 4.7.4 on page 140 for detailed information.

In this mode of operation, timer/counter 2 can be used as a simple system timer, an external event counter or a pulse accu-

mulate counter. Counter TnCNT2 counts down with the clock selected via the counter 2 clock selector, and TnCNT2 can be

configured to generate an interrupt on underflow if the interrupt is enabled by TnDIEN bit. See Section 4.7.4 on page 140

for detailed information.

Mode 2, Dual Input Capture

Dual Input Capture mode can be used to precisely measure the frequency of an external clock that is slower than the se-

lected clock source frequency or to measure the elapsed time between external events. A transition received on the TAn or

TBn pin causes a transfer of timer/counter 1 contents to TnCRA or TnCRB register, respectively. In this mode, timer/counter

2 can be utilized as a system timer that is pre-loaded by software and generates an interrupt on underflow.

Figure 48 shows a block diagram of the timer operating in mode 2. In this mode of operation, the timebase of the capture

timer is formed by counter 1, which counts down with the clock selected via the counter 1 clock selector. In Dual Input Cap-

ture mode, TAn and TBn pins function as capture inputs. A transition received on TAn pin causes a transfer of the timer

contents to TnCRA register. Similarly, a transition received on the TBn pin causes a transfer of the timer contents to TnCRB

register. TAn and TBn inputs can be configured to perform a counter preset to FFFF16 on reception of a valid capture event.

Reload A = Time 1

Timer/Counter 1

Reload B = Time 2

Timer 1

Clock

Underflow

TAn

TAIEN

TAPND

TnCNT1

TnCRA

TnCRB

TBIEN

TBPND

Timer

Interrupt 1

Timer

Interrupt 1

TAEN

Timer/Counter 2

TnCNT2

Timer 2

Clock

TDIEN

TDPND

Timer

Interrupt 2

TBn

Clock

Selector

Underflow

Figure 47. Mode 1, PWM and Counter

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