PC87591L datasheet(130/437 Pages) NSC

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Embedded Controller Modules (Continued)

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130

Revision 1.07

PS/2 Control Register (PSCON)

The PSCON register is an 8-bit read/write register. It controls the operation of the PS/2 interface by enabling it and controlling

the data transfer direction. On reset, PSCON is set to 0016.

Location: 00 FE8416

Type: R/W

5-3

ACH (Active Channel). Deﬁnes which of the PS/2 channels is currently active (i.e., a start bit was detected). In

case more than one channel become active simultaneously, only the one with the highest priority (lowest

number) is ﬂagged.

Bits

5 4 3

Description

0 0 0:

None of the channels is active

0 0 1:

Channel 1

0 1 0:

Channel 2

1 0 0:

Channel 3

1 0 1:

Channel 4

RFERR (Receive Frame Error).

When set to 1, indicates that the stop bit in a received frame was detected low instead of high.

Reserved.

Bit

76543210

Name

WPUEN

IDB

HDRV

XMT

Reset

00000000

Bit

Description

EN (Shift Mechanism Enable).

0: The hardware shift mechanism is disabled and the software controls and monitors the PS/2 signals using

PSOSIG and PSISIG registers.

1: The hardware shift mechanism is enabled. The enabled channels are controlled by PSOSIG, and Transmit/Re-

ceive mode is controlled by the XMT bit.

XMT (Transmit Enable).

0: Receive mode.

1: Causes the PS/2 interface to enter Transmit mode.

3-2

HDRV (High Drive). Deﬁnes the quasi-bidirectional buffers’ behavior on transition from low to high. HDRV

deﬁnes the period of time for which the output is pulled high with a low-impedance drive (when the PC87591x

changes the output level from low to high). This period is a function of the PC87591x clock as follows:

Bits

3 2

Description

0 0:

Disabled

0 1:

Low-impedance drive for one clock cycle

1 0:

Low-impedance drive for two clock cycles

1 1:

Low-impedance drive for three clock cycles

Bit

Description

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